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Author: search.filters.author.Chivapreecha, SorawatSubject: search.filters.subject.LMS algorithm

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    Distributed arithmetic LMS adaptive filter implementation without look-up table
    (2012-10-02)
    Trakultritrung, Anirut
    ;
    Thanangchusin, Ekkawin
    ;
    Chivapreecha, Sorawat
    This paper presents an implementation of least mean squared (LMS) adaptive filter using distributed arithmetic (DA) for hardware realization. Coefficient-distributive DA will be used instead of conventional DA for more appropriation to use with adaptive filter that filter coefficients are varied by time. Moreover, adder network and multiplexer structure will be used in coefficient-distributive DA which makes the proposed LMS adaptive filter be multiplierless digital filter and also without using look-up table (LUT). The VHDL is used for hardware design and then synthesis and configure onto FPGA for real-time adaptive filtering experiment. Finally, experimental and simulation results are shown to ensure our proposed LMS adaptive filter can work. © 2012 IEEE.
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    Adaptive equalization architecture using distributed arithmetic for partial response channels
    (2006-12-01)
    Chivapreecha, Sorawat
    ;
    Jaruvarakul, Aungkana
    ;
    Jaruvarakul, Nivat
    ;
    Dejhan, Kobchai
    This paper proposes a design and implementation of transversal adaptive digital filter using LMS (Least Mean Squares) adaptive algorithm. The filter structure is based on Distributed Arithmetic (DA), which is able to calculate the inner product by shifting, and accumulating of partial products and storing in look-up table, also the desired adaptive digital filter will be multiplierless filter. In addition, the hardware implementation uses VHDL (Very high-speed integrated circuit Hardware Description Language) and synthesis using FLEX10K Altera FPGA (Field Programmable Gate Array) as target technology and uses Leonardo Spectrum and MAX+plusII program for overall development. The results of this design are shown that the speed performance and used area of FPGA. The experimental results are presented to demonstrate the feasibility of the desired adaptive digital filter.. © 2006 IEEE.