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Author: search.filters.author.Chuenarom, S.

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    Low power current-mode algorithmic ADC in half flash (BCD)
    (2006-12-01)
    Chuenarom, S.
    ;
    Maitreechit, S.
    ;
    Roengruen, P.
    ;
    Tipsuwarnpron, V.
    This paper presents a principle of analog to digital converter (ADC) based on current mode half flash (BCD). This circuit can be converted to 4-bit output at each moment, and multiple output bit numbers by serial connection. It use a current injection technique to increase the speed of current mirrors, low power and algorithmic ADC application is presented. A current mode, the active current mirror and current comparators that controlled reference current by W/L ratio, has been used. Its feasibility agrees with simulation results of PSPICE program. The circuit design used CMOS 0.5μm which is capable to the slowest conversion time is less than 5.2nS , resulting in a conversion rate of more than 195 MHz , power consumed 1mW , input current 0-60 μA and single 2.5V supply. ©2006 IEEE.
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    Application techniques for high performance ADC
    (2006-12-01)
    Chuenarom, S.
    ;
    Tipsuwampron, V.
    A current-mode technique for the design of algorithmic ADC is presented. The necessary voltage swing is given dynamic range to be reduced at the same time. It uses CMOS op-amp common with a current injection technique. The advantage of op-amp reduces current mismatches due to the device finite output resistance and injection current to increase the speed of current mirrors. In this paper that the advantages and disadvantages of different ADC algorithmic is designed of new algorithmic ADC for the output current of comparator. The objective is the development an increase performance ADC. The 6-bit ADC is implemented in 0.25μm CMOS technology. It has a conversion rate of 7.3MHz, a low power 2.5V, a power dissipation of 0.83mW with the differential nonlinearity (DNL,) of 0.29LSB and integral nonlinearity (INL) of 0.16LSB. © 2006 IEEE.
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    Algorithmic ADC using current mode without DAC
    (2002-01-01)
    Tipsuwanporn, V.
    ;
    Numsomran, A.
    ;
    Chuchotsakunleot, W.
    ;
    Chuenarom, S.
    ;
    Maitreechit, S.
    This paper presents a principle of analog to digital conversion (ADC) based on a current mode circuit without DAC. For example, in this circuit the input value can be converted to a 4 bit output at each moment, and multiple output bit numbers by serial connection. In this current mode, the active current mirror and current comparators control the reference current by adjusting the W/L ratio. Its feasibility agrees with simulation results by the PSPICE program. The circuit design used a CMOS 0.5 μm process which is capable of converting 4 bits in 50 ns, with a power consumption of 0.127 mW, input current of 0-100 μA and single 3 V supply. From simulation testing, the conversion rate is faster than other methods using the same parameters.
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    Half flash ADC 4-bit without DAC
    (2001-12-01)
    Tipsuwanporn, V.
    ;
    Chuenarom, S.
    ;
    Junkrob, N.
    ;
    Chuchotsakunleot, W.
    ;
    Roengruen, P.
    This paper presents a principle of parallel Analog To Digital Conversion (ADC) based on current mode HALF FLASH ADC. This circuit can be converted to 4-bit output at each moment, and multiple output bit numbers by serial connection. A current mode, the active current mirror and current comparators that controlled reference current by W/L ratio, has been used. Its feasibility agrees with simulation results of PSPICE program. The circuit design used CMOS 0.8 μm which is capable to convert 4 -bit in 50 nS, power consumed 0.127 mW, input current 0-100 μA and single 3V supply. From simulation testing, the conversion rate is faster than other method.
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    Independent BRM multi patterns with VFC
    (2000-12-01)
    Tipsuwanporn, V.
    ;
    Tirasesth, K.
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    Sattho, U.
    ;
    Witheephanich, K.
    ;
    Chuenarom, S.
    In this paper voltage-to-frequency conversion (VFC) circuit with Binary Rate Multipliers (BRM) output is presented. We first analyze spectrum value and percentage of Binary Bit Rate (BBR) power then reject the repeated power values, and select only one BBR signal to construct BRM by linear combination. A VFC design with 1 to 5 volts (Vin) and ±2.5 volts (Vout) can generate BRM pattern (0 Hz - 39.0625 kHz) in sine, triangular, saw-tooth and square waveform. The average value of VFC output signal is fedback to input of the VFC in order to stabilize pattern for BRM transmission. The output patterns and frequencies can be controlled either independently or simultaneously.