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Author: search.filters.author.Jongsataporn, ThitaphanSubject: search.filters.subject.Bilinear Pascal matrix

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    The matrix-based design and realization of digital parametric equalizer
    (2021-05-01)
    Jongsataporn, Thitaphan
    ;
    Chivapreecha, Sorawat
    This paper presents the design of a digital parametric equalizer based on matrix design equations and their corresponding digital filter structures. Matrix-based design equations are modified from the so called bilinear Pascal matrix for s-z transformation, appended with modifications in the feed-forward path of direct form-II digital filter structure based on consideration of standard biquadratic filters compared with peaking filter, lowpass shelving filter, and highpass shelving filter, as well as the proposed improvement procedures. Consequently, matrix design equations and their corresponding multiple outputs filter structure realizations for digital version of peaking, lowpass shelving, and highpass shelving filters can be achieved. The matrix-based design method and the proposed filter structure are consistent in terms of implementation because the main mechanism of a digital filter is determined by its filter structure, while filter coefficients are calculated from the matrix equation that corresponds to such structure. Digital filter characteristic can be determined or adjusted by updating new filter coefficients through matrix computation. The proposed peaking, lowpass shelving, and highpass shelving digital filters can be cascaded for use as a digital parametric equalizer. Design examples and the resulting frequency responses are shown as well as further explanation of hardware implementation for real-time digital parametric equalizer on STM32F769 processor. The simulation results and actual hardware frequency response measurements are compared to confirm the success of the proposed matrix-based design method and its implementation.
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    An Implementation of Digital Parametric Equalizer on STM32 Processor
    (2020-06-01)
    Jongsataporn, Thitaphan
    ;
    Cheevapreecha, Sorawat
    This paper presents design and implementation of digital parametric equalizer. The design method starts with analog filter prototypes consisting of peak filters, low-pass shelving filter, and high-pass shelving filter in the form of transfer function in the s-domain. The bilinear Pascal matrix is used for converting the transfer function in s-domain using bilinear s-z transformation to obtain all three types of digital filter as a transfer function in z-domain. By cascading of these digital filters result in obtaining a digital parametric equalizer. The simulation results are shown and hardware implementation on STM32F769 for real-time testing is also demonstrated to ensure the successfully of the proposed design and implementation.