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Embedded Hardware Implementation of Noise Gate on STM32 Processor Using MATLAB/Simulink
(2025-01-01)
Jongsataporn, Thitaphan
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Chivapreecha, Sorawat
This paper presents a model-based approach for developing a digital signal processing (DSP) system, specifically focusing on a Noise Gate application, using MATLAB/Simulink, and deploying it on the STM32F769I-Discovery board. The study thoroughly examines the advantages of model-based hardware implementation, particularly in facilitating rapid prototyping for real-time applications in educational contexts. The STM32F769I is powered by a high-performance Arm® Cortex®-M7 core, which can execute DSP instructions efficiently. Its ample memory and built-in debugging tools enhance its suitability for complex signal processing tasks. The implementation leverages MATLAB/Simulink and its robust compatibility with the STM32 hardware, allowing for seamless software and hardware component integration. The powerful model-based development features streamline the transition from simulation to physical hardware, reducing development time and enhancing reliability. The Noise Gate application is designed to control audio signals effectively, eliminating unwanted background noise through user-defined parameters such as threshold, attack time, and release time, which optimize performance based on specific audio environments. Additionally, the design applies a first-order IIR low-pass as a smoothing filter, which dynamically adjusts the gain according to the characteristics of the incoming audio signal. This ensures gradual opening and closing of the gate, resulting in smoother audio transitions. The results demonstrate significant noise suppression and overall audio quality enhancement, highlighting the practicality of employing model-based design methodologies for DSP applications. Furthermore, the insights gained from this study contribute to efficient hardware prototype development and offer implications for future projects in the field of digital signal processing.
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Tunable 1st Order IIR Phase Shifter Design and Implementation
(2024-01-01)
Chivapreecha, Sorawat
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Jongsataporn, Thitaphan
This paper presents a new phase shifter which is a first-order infinite impulse response (IIR) filter that can shift phase both in phase-lead (0° to+180°) and phase-lag (-180° to 0°) fashion. Moreover, continuous phase tuning is also proposed in our phase shifter. The z-transform pair of phase-shifted cosine signal is utilized as the origin, then factorization of such term can give transfer function of first-order IIR phase shifter. The filter structure realization of the tunable phase shifter will be shown and applied with a digital cosine oscillator. Both simulation and hardware experiments can show phase-shifted signals in real-time controlled by phase-tuning parameters compared with a cosine reference signal as a demonstration. The allpass phase shifter will be used as a benchmark, and trade-off analysis using the proposed phase shifter will also be discussed.
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Design and Implementation of Multiphase Digital Oscillator
(2024-01-01)
Jongsataporn, Thitaphan
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Yospanya, Poonna
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Chivapreecha, Sorawat
This paper presents a design and implementation of the multiphase digital oscillator, which can determine the initial phase of multi-output signals to desired initial phases. The proposed system consists of biquad digital oscillator to oscillate the reference signal, and the new phase shifters which are first order IIR filters that can shift the phase of signals at a specified frequency to give them the desired phases. Design example and simulation results will be shown. Moreover, real-time hardware implementation on STM32 digital signal processor can be demonstrated to confirm the proposed design can work with hardware experimental results.
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The matrix-based design and realization of digital parametric equalizer
(2021-05-01)
Jongsataporn, Thitaphan
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Chivapreecha, Sorawat
This paper presents the design of a digital parametric equalizer based on matrix design equations and their corresponding digital filter structures. Matrix-based design equations are modified from the so called bilinear Pascal matrix for s-z transformation, appended with modifications in the feed-forward path of direct form-II digital filter structure based on consideration of standard biquadratic filters compared with peaking filter, lowpass shelving filter, and highpass shelving filter, as well as the proposed improvement procedures. Consequently, matrix design equations and their corresponding multiple outputs filter structure realizations for digital version of peaking, lowpass shelving, and highpass shelving filters can be achieved. The matrix-based design method and the proposed filter structure are consistent in terms of implementation because the main mechanism of a digital filter is determined by its filter structure, while filter coefficients are calculated from the matrix equation that corresponds to such structure. Digital filter characteristic can be determined or adjusted by updating new filter coefficients through matrix computation. The proposed peaking, lowpass shelving, and highpass shelving digital filters can be cascaded for use as a digital parametric equalizer. Design examples and the resulting frequency responses are shown as well as further explanation of hardware implementation for real-time digital parametric equalizer on STM32F769 processor. The simulation results and actual hardware frequency response measurements are compared to confirm the success of the proposed matrix-based design method and its implementation.
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A Deep Learning Approach to Digital Filter Parameter Estimation Based on Amplitude Responses
(2021-01-21)
Yospanya, Poonna
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Chivapreecha, Sorawat
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Jongsataporn, Thitaphan
This paper presents our attempt to tackle the problem of digital filter type and parameter estimation given a set of points sampled from a filter frequency response. We compared results from various multilayer perceptron and convolutional neural network configurations. The results suggest that a convolutional neural network generally produces faster convergence with a lower loss at the same number of epochs than a multilayer perceptron network. However, the maximum amplitude response error, which is the true performance metrics, can be comparable in some cases. A combination of multiple best-performing configurations for different tasks is used to assemble the final model.
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An Implementation of Digital Parametric Equalizer on STM32 Processor
(2020-06-01)
Jongsataporn, Thitaphan
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Cheevapreecha, Sorawat
This paper presents design and implementation of digital parametric equalizer. The design method starts with analog filter prototypes consisting of peak filters, low-pass shelving filter, and high-pass shelving filter in the form of transfer function in the s-domain. The bilinear Pascal matrix is used for converting the transfer function in s-domain using bilinear s-z transformation to obtain all three types of digital filter as a transfer function in z-domain. By cascading of these digital filters result in obtaining a digital parametric equalizer. The simulation results are shown and hardware implementation on STM32F769 for real-time testing is also demonstrated to ensure the successfully of the proposed design and implementation.
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A Simple Tunable Biquadratic Digital Bandpass Filter Design for Spectrum Sensing in Cognitive Radio
(2020-06-01)
Sutthikarn, Pemmavit
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Chivapreecha, Sorawat
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Trirat, Akraphon
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Jongsataporn, Thitaphan
This article presents a design and realization of tunable digital bandpass filter based on using biquadratic filter for spectrum sensing in cognitive radio. The biquadratic bandpass digital filter structure has shown and after that the tunable approach will be derived. The bandwidth and center frequency of the proposed tunable biquadratic digital bandpass filter can be tuned by tuning parameters. In each band, energy detection by spectrum sensing method will be used by cognitive radio users (CRU) for recognize the frequency spectrum of primary user (PU). If there are not having any PU in that band, the status of band will set to spectrum hole. Eventually, CRU can utilize this channel.
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Tunable bandpass/bandstop digital filters basedon 1st-order allpass network instead of unit delay
(2019-07-01)
Sutthikarn, Pemmavit
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Chivapreecha, Sorawat
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Jongsataporn, Thitaphan
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Trirat, Akraphon
This paper presents a design and realization of tunable bandpass and bandstop digital filters based on using tunable digital lowpass and highpass filters. The frequency response of both digital lowpass and highpass filters which called prototype filters can be changed/tuned by replacing unit delay elements in filter structure with 1<sup>st</sup>-order allpass network. From the tunable digital lowpass and highpass filters, the cascade connection of them can give tunable bandpass filter, the parallel connection can give tunable bandstop filter. The conditions of using proposed tunable bandpass/bandstop filters will be analyzed and explained in this work. A high flexibility of tuning both center frequency and bandwidth can be achieved from the proposed design and realization. Simulation results also be compared with experimental results from hardware implementation on FPGA using NI-myRIO device to ensure that the obtained frequency responses are correspondence.
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Mathematical model of audiogram with second order recursive system
(2011-12-01)
Jongsataporn, Thitaphan
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Yimman, Surapun
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Praesomboon, Sukanya
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Dejhan, Kobchai
This research presents a new design of mathematical model of audiogram by using the second order recursive all-pass filter and least square approximation technique. The initial step is to design the system function of second order all-pass filter that have the pole-zero angle corresponds with the minimum and maximum amplitude of audiogram. After that, using the least square approximation technique to find the distance of pole and zero between the origin. For the appropriate zero position used least square technique. The magnitude response of propose design was simulated by MATLAB software, the simulation result have show that this method could perform be similar to the audiogram. © 2011 IEEE.
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A web-based integrated medical information system for telepathology
(2010-12-01)
Jongsataporn, Thitaphan
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Yimmun, Surapun
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Suapang, Piyamas
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Boontawan, Rodjarin
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Dejhan, Kobchai
The design and implementation of A Web-based Integrated Medical Information System for Telepathology which server was developed using software such as Borland C++ Builder 5.0, PHP and MySQL for image archive, image compression, image processing and image transmission. The system provides the following facilities: (1) DICOM-format image archive. (2) Medical Image Compression based on JPEG and JPEG2000. and (3) DICOM viewer. The results shown that (1) our system can also convert the image data both single frame and multiframe in normal or automatic DICOM process into the standard DICOM 3.0 format without altering the image data. (2) The resulting images are then compressed with two different techniques - JPEG and JPEG2000. The significant advantage of JPEG2000 over normal JPEG is that the error from JPEG2000 compression is smaller than the error from JPEG. Nevertheless, both methods share a similar mishap; when the compression ratio increases, they both generate more error than the processes on lower compression ratio. And (3) our system can open single frame and continuous frames, each of which can exhibit information in .dcm file format with no distortion and digital image processing based on local contrast enhancement, adaptive interpolators techniques and cine loop. The system has been developed and provided medical image services over long distance which showed the usefulness of our approach.

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