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Author: search.filters.author.Khateb, FabianSubject: search.filters.subject.Bulk-driven MOS

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    Low-voltage low-power bulk-driven analog median filter
    (2016-05-01)
    Khateb, Fabian
    ;
    Kumngern, Montree
    ;
    Dabbous, Salma Bay Abo
    ;
    Kulej, Tomasz
    This paper presents low-voltage (LV) low-power (LP) voltage-mode analog median filter based on winner-take-all (WTA) and loser-take-all (LTA) circuits. The LTA and WTA CMOS structures are performed utilizing bulk-driven (BD) MOS transistor (MOST) technique, enabling circuits to operate under low supply voltage of only ±0.25 V and consume extremely low-power in micro range. In addition to the simple topology of the proposed circuits, they provide high accuracy. Moreover, the common mode voltage range is near rail-to-rail. Eventually, to verify the functionality of the proposed circuits, the simulation results are carried out in Cadence environment using triple-well 0.18 μm CMOS process.
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    1-V Inverting and Non-inverting Loser-Take-All Circuit and Its Applications
    (2016-05-01)
    Khateb, Fabian
    ;
    Kumngern, Montree
    ;
    Kulej, Tomasz
    A new solution for a non-conventional loser-take-all (LTA) circuit is proposed in the paper. The circuit possesses several inverting and non-inverting input terminals and an additional current output, which increases its versatility and allows simplifying its possible applications. In order to show its usefulness and versatility, several new applications of the proposed LTA have also been developed, including a simple digital-to-analog converter, an n-bit programmable adder/summer, a chopper modulator and a precision rectifier. The LTA has been designed and fabricated with a 0.35  (Formula presented.) CMOS I3T25 AMIS process, exploiting the recently proposed bulk-driven quasi-floating-gate technique. The LTA circuit operates from 1 V supply and dissipates 74  (Formula presented.) of power. The simulations performed in Cadence environment and the measurements of a real chip confirm the attractive features of the proposed LTA.
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    1 V Rectifier Based on Bulk-Driven Quasi-Floating-Gate Differential Difference Amplifiers
    (2015-07-18)
    Khateb, Fabian
    ;
    Vlassis, Spyridon
    ;
    Kumngern, Montree
    ;
    Psychalinos, Costas
    ;
    Kulej, Tomasz
    This paper presents experimental results for a low-voltage (LV) low-power (LP) voltage rectifier realization, employing two differential difference amplifiers (DDA) as active elements.The proposed DDA is based on the recently presented technique named bulk-driven quasi-floating-gate that enables the circuit to work with 1 V power supply voltage, threshold-to-supply (Formula presented.) ratio and modulation index factor (Formula presented. equal to 70 and 90 %, respectively. The competitive features of the proposed structure compared with other state-of-the-art circuits are the capability for working under LV supply, with extended common mode voltage range and improved input transconductance. The proposed circuit was designed, simulated, and fabricated employing the Cadence platform and MOS transistors models provided by the 0.35 μm CMOS AMIS process. The total chip area was 213 × 266 μ<sup>m2</sup>. The provided simulation and experimental results prove the attractive performances of the proposed rectifier topology.
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    Ultra low-voltage low-power current conveyor transconductance amplifier
    (2015-07-01)
    Khateb, Fabian
    ;
    Kumngern, Montree
    ;
    Dabbous, Salma Bay Abo
    ;
    Kulej, Tomasz
    ;
    Lahiri, Abhirup
    This paper presents ultra low-voltage (LV) low-power (LP) CMOS structure for Current Conveyor Transconductance Amplifier (CCTA). The proposed structure is performed using recently presented technique named bulk-driven quasi-floating gate (BD-QFG) enabling the CCTA to operate at low supply voltage ±0.3 V with low-power consumption in the micro range of 34 μW. Moreover, the proposed circuit provides adjustable transconductance via external grounded resistor. In addition to the topology simplicity, the proposed circuit offers high linearity and extended range of transconductance controlling. Two new figure of merit (FOM) are used to characterize the performance of the design and prove its effectiveness as compared to other. Eventually, to verify the functionality of the circuit, two current mode multi-function biquad filters are included as examples of application. The simulations are performed in PSPICE environment using the 0.18 μm CMOS n-well process from TSMC.
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    Digitally programmable low-voltage highly linear transconductor based on promising CMOS structure of differential difference current conveyor
    (2015-07-01)
    Khateb, Fabian
    ;
    Lahiri, Abhirup
    ;
    Psychalinos, Costas
    ;
    Kumngern, Montree
    ;
    Kulej, Tomasz
    A digitally programmable low-voltage highly linear transconductor (G<inf>m</inf> stage) realization, using a promising CMOS structure of differential difference current conveyor (DDCC) and a R-2R ladder network, is introduced in this paper. Thanks to the efficiency of the DDCC CMOS structure, the transconductor exhibits excellent linearity in a wide range of the input voltage and its transconductance value is digitally programmable by the use of a R-2R ladder network. The CMOS structure of the DDCC is based on the latest bulk-driven quasi-floating-gate technique and hence it is capable to work under low-voltage power supply of ±0.5 V and consumes 36 μW of power. The differential input MOS transistor pairs of the proposed structure are simultaneously driven from bulk and quasi-floating-gate terminals; this leads to an increased value of the voltage gain, bandwidth, and input common-mode voltage range. The last one is the main benefit of this structure in comparison to already existing solutions. The proposed CMOS structure of the DDCC was designed and fabricated using 0.35 μm CMOS AMIS process with total chip area 213 μm × 266 μm. As an application example, a digitally programmable universal filter using three DDCCs and two grounded capacitors is presented.