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Author: search.filters.author.Lahiri, AbhirupSubject: search.filters.subject.Quasi-floating-gate MOS

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    Ultra low-voltage low-power current conveyor transconductance amplifier
    (2015-07-01)
    Khateb, Fabian
    ;
    Kumngern, Montree
    ;
    Dabbous, Salma Bay Abo
    ;
    Kulej, Tomasz
    ;
    Lahiri, Abhirup
    This paper presents ultra low-voltage (LV) low-power (LP) CMOS structure for Current Conveyor Transconductance Amplifier (CCTA). The proposed structure is performed using recently presented technique named bulk-driven quasi-floating gate (BD-QFG) enabling the CCTA to operate at low supply voltage ±0.3 V with low-power consumption in the micro range of 34 μW. Moreover, the proposed circuit provides adjustable transconductance via external grounded resistor. In addition to the topology simplicity, the proposed circuit offers high linearity and extended range of transconductance controlling. Two new figure of merit (FOM) are used to characterize the performance of the design and prove its effectiveness as compared to other. Eventually, to verify the functionality of the circuit, two current mode multi-function biquad filters are included as examples of application. The simulations are performed in PSPICE environment using the 0.18 μm CMOS n-well process from TSMC.
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    Digitally programmable low-voltage highly linear transconductor based on promising CMOS structure of differential difference current conveyor
    (2015-07-01)
    Khateb, Fabian
    ;
    Lahiri, Abhirup
    ;
    Psychalinos, Costas
    ;
    Kumngern, Montree
    ;
    Kulej, Tomasz
    A digitally programmable low-voltage highly linear transconductor (G<inf>m</inf> stage) realization, using a promising CMOS structure of differential difference current conveyor (DDCC) and a R-2R ladder network, is introduced in this paper. Thanks to the efficiency of the DDCC CMOS structure, the transconductor exhibits excellent linearity in a wide range of the input voltage and its transconductance value is digitally programmable by the use of a R-2R ladder network. The CMOS structure of the DDCC is based on the latest bulk-driven quasi-floating-gate technique and hence it is capable to work under low-voltage power supply of ±0.5 V and consumes 36 μW of power. The differential input MOS transistor pairs of the proposed structure are simultaneously driven from bulk and quasi-floating-gate terminals; this leads to an increased value of the voltage gain, bandwidth, and input common-mode voltage range. The last one is the main benefit of this structure in comparison to already existing solutions. The proposed CMOS structure of the DDCC was designed and fabricated using 0.35 μm CMOS AMIS process with total chip area 213 μm × 266 μm. As an application example, a digitally programmable universal filter using three DDCCs and two grounded capacitors is presented.