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Author: search.filters.author.Maitreechit, S.

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    Low power current-mode algorithmic ADC in half flash (BCD)
    (2006-12-01)
    Chuenarom, S.
    ;
    Maitreechit, S.
    ;
    Roengruen, P.
    ;
    Tipsuwarnpron, V.
    This paper presents a principle of analog to digital converter (ADC) based on current mode half flash (BCD). This circuit can be converted to 4-bit output at each moment, and multiple output bit numbers by serial connection. It use a current injection technique to increase the speed of current mirrors, low power and algorithmic ADC application is presented. A current mode, the active current mirror and current comparators that controlled reference current by W/L ratio, has been used. Its feasibility agrees with simulation results of PSPICE program. The circuit design used CMOS 0.5μm which is capable to the slowest conversion time is less than 5.2nS , resulting in a conversion rate of more than 195 MHz , power consumed 1mW , input current 0-60 μA and single 2.5V supply. ©2006 IEEE.
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    Improved speed rate in current mode algorithmic ADC
    (2005-12-01)
    Tipsuwarnpron, V.
    ;
    Roengruen, P.
    ;
    Chuchotsakunleot, W.
    ;
    Maitreechit, S.
    A low power current-mode analog to digital converter suitable for equipment are required low voltage, low power (ADC). It uses a quartzite level with current injection technique to increase the speed of current mirrors. And this method to reduce the required input signal for a given range and higher operating speeds. In this paper, the feasibility of current-mode algorithmic ADC is demonstrated and advantages of various 2 techniques for use in the converters are considered. Experimental results for 4-bits algorithmic ADC using a 0.8 μm CMOS technology are reported, including power consumption.
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    Algorithmic ADC using current mode without DAC
    (2002-01-01)
    Tipsuwanporn, V.
    ;
    Numsomran, A.
    ;
    Chuchotsakunleot, W.
    ;
    Chuenarom, S.
    ;
    Maitreechit, S.
    This paper presents a principle of analog to digital conversion (ADC) based on a current mode circuit without DAC. For example, in this circuit the input value can be converted to a 4 bit output at each moment, and multiple output bit numbers by serial connection. In this current mode, the active current mirror and current comparators control the reference current by adjusting the W/L ratio. Its feasibility agrees with simulation results by the PSPICE program. The circuit design used a CMOS 0.5 μm process which is capable of converting 4 bits in 50 ns, with a power consumption of 0.127 mW, input current of 0-100 μA and single 3 V supply. From simulation testing, the conversion rate is faster than other methods using the same parameters.
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    Half flash ADC 4-bit without DAC
    (2001-12-01)
    Tipsuwanporn, V.
    ;
    Chuenarom, S.
    ;
    Junkrob, N.
    ;
    Chuchotsakunleot, W.
    ;
    Roengruen, P.
    This paper presents a principle of parallel Analog To Digital Conversion (ADC) based on current mode HALF FLASH ADC. This circuit can be converted to 4-bit output at each moment, and multiple output bit numbers by serial connection. A current mode, the active current mirror and current comparators that controlled reference current by W/L ratio, has been used. Its feasibility agrees with simulation results of PSPICE program. The circuit design used CMOS 0.8 μm which is capable to convert 4 -bit in 50 nS, power consumed 0.127 mW, input current 0-100 μA and single 3V supply. From simulation testing, the conversion rate is faster than other method.