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Author: search.filters.author.Psychalinos, CostasSubject: search.filters.subject.Bulk-driven MOS

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    1 V Rectifier Based on Bulk-Driven Quasi-Floating-Gate Differential Difference Amplifiers
    (2015-07-18)
    Khateb, Fabian
    ;
    Vlassis, Spyridon
    ;
    Kumngern, Montree
    ;
    Psychalinos, Costas
    ;
    Kulej, Tomasz
    This paper presents experimental results for a low-voltage (LV) low-power (LP) voltage rectifier realization, employing two differential difference amplifiers (DDA) as active elements.The proposed DDA is based on the recently presented technique named bulk-driven quasi-floating-gate that enables the circuit to work with 1 V power supply voltage, threshold-to-supply (Formula presented.) ratio and modulation index factor (Formula presented. equal to 70 and 90 %, respectively. The competitive features of the proposed structure compared with other state-of-the-art circuits are the capability for working under LV supply, with extended common mode voltage range and improved input transconductance. The proposed circuit was designed, simulated, and fabricated employing the Cadence platform and MOS transistors models provided by the 0.35 μm CMOS AMIS process. The total chip area was 213 × 266 μ<sup>m2</sup>. The provided simulation and experimental results prove the attractive performances of the proposed rectifier topology.
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    Digitally programmable low-voltage highly linear transconductor based on promising CMOS structure of differential difference current conveyor
    (2015-07-01)
    Khateb, Fabian
    ;
    Lahiri, Abhirup
    ;
    Psychalinos, Costas
    ;
    Kumngern, Montree
    ;
    Kulej, Tomasz
    A digitally programmable low-voltage highly linear transconductor (G<inf>m</inf> stage) realization, using a promising CMOS structure of differential difference current conveyor (DDCC) and a R-2R ladder network, is introduced in this paper. Thanks to the efficiency of the DDCC CMOS structure, the transconductor exhibits excellent linearity in a wide range of the input voltage and its transconductance value is digitally programmable by the use of a R-2R ladder network. The CMOS structure of the DDCC is based on the latest bulk-driven quasi-floating-gate technique and hence it is capable to work under low-voltage power supply of ±0.5 V and consumes 36 μW of power. The differential input MOS transistor pairs of the proposed structure are simultaneously driven from bulk and quasi-floating-gate terminals; this leads to an increased value of the voltage gain, bandwidth, and input common-mode voltage range. The last one is the main benefit of this structure in comparison to already existing solutions. The proposed CMOS structure of the DDCC was designed and fabricated using 0.35 μm CMOS AMIS process with total chip area 213 μm × 266 μm. As an application example, a digitally programmable universal filter using three DDCCs and two grounded capacitors is presented.