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    Item type:Publication,
    Design of combinational logic training system using FPGA
    (2010-12-01)
    Sothong, Sujittra
    ;
    Chayratsami, Pornpimon
    This paper describes a design of a training system for a combinational logic design course. The goals of this design are to reduce a cost of the system and to lower the lost and damage of TTL elements used in a digital laboratory currently. The system uses a Field Programmable Gate Array (FPGA) as a processor containing basic logic gates, and uses a microcontroller as a gate selector. The training system consists of a system unit base, 17 basic logic gate models, and 10 lab sheets. The system is evaluated in terms of quality and using suitability of the system by experts and instructors who work with technical schools in Thailand and have been involving and teaching a combinational logic design course for at least 5 years. The results show that the system is rated to have a very good quality and is suitable for being used as a training system in a combinational logic course with inexpensive cost. © 2010 IEEE.