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    Embedded Hardware Implementation of Noise Gate on STM32 Processor Using MATLAB/Simulink
    (2025-01-01)
    Jongsataporn, Thitaphan
    ;
    Chivapreecha, Sorawat
    This paper presents a model-based approach for developing a digital signal processing (DSP) system, specifically focusing on a Noise Gate application, using MATLAB/Simulink, and deploying it on the STM32F769I-Discovery board. The study thoroughly examines the advantages of model-based hardware implementation, particularly in facilitating rapid prototyping for real-time applications in educational contexts. The STM32F769I is powered by a high-performance Arm® Cortex®-M7 core, which can execute DSP instructions efficiently. Its ample memory and built-in debugging tools enhance its suitability for complex signal processing tasks. The implementation leverages MATLAB/Simulink and its robust compatibility with the STM32 hardware, allowing for seamless software and hardware component integration. The powerful model-based development features streamline the transition from simulation to physical hardware, reducing development time and enhancing reliability. The Noise Gate application is designed to control audio signals effectively, eliminating unwanted background noise through user-defined parameters such as threshold, attack time, and release time, which optimize performance based on specific audio environments. Additionally, the design applies a first-order IIR low-pass as a smoothing filter, which dynamically adjusts the gain according to the characteristics of the incoming audio signal. This ensures gradual opening and closing of the gate, resulting in smoother audio transitions. The results demonstrate significant noise suppression and overall audio quality enhancement, highlighting the practicality of employing model-based design methodologies for DSP applications. Furthermore, the insights gained from this study contribute to efficient hardware prototype development and offer implications for future projects in the field of digital signal processing.
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    The matrix-based design and realization of digital parametric equalizer
    (2021-05-01)
    Jongsataporn, Thitaphan
    ;
    Chivapreecha, Sorawat
    This paper presents the design of a digital parametric equalizer based on matrix design equations and their corresponding digital filter structures. Matrix-based design equations are modified from the so called bilinear Pascal matrix for s-z transformation, appended with modifications in the feed-forward path of direct form-II digital filter structure based on consideration of standard biquadratic filters compared with peaking filter, lowpass shelving filter, and highpass shelving filter, as well as the proposed improvement procedures. Consequently, matrix design equations and their corresponding multiple outputs filter structure realizations for digital version of peaking, lowpass shelving, and highpass shelving filters can be achieved. The matrix-based design method and the proposed filter structure are consistent in terms of implementation because the main mechanism of a digital filter is determined by its filter structure, while filter coefficients are calculated from the matrix equation that corresponds to such structure. Digital filter characteristic can be determined or adjusted by updating new filter coefficients through matrix computation. The proposed peaking, lowpass shelving, and highpass shelving digital filters can be cascaded for use as a digital parametric equalizer. Design examples and the resulting frequency responses are shown as well as further explanation of hardware implementation for real-time digital parametric equalizer on STM32F769 processor. The simulation results and actual hardware frequency response measurements are compared to confirm the success of the proposed matrix-based design method and its implementation.