KMITL

Permanent URI for this communityhttps://dspace.kmitl.ac.th/handle/123456789/1

Browse

Search Results

Now showing 1 - 7 of 7

Some of the metrics are blocked by your
consent settings
Evaluation of a three-phase three-level ZVZCS DC-DC converter using phase-shift PWM strategy
(2017-09-01)
Kongwirat, Thammachat
;
Jangwanitlert, Anuwat
This paper presents the evaluation of a three-phase three-level DC-DC converter which achieves the soft switching condition for all switches in the circuit and uses the phase-shift PWM strategy to adjust electric power at the output side. According to the analysis, the operation modes can be categorized into two cases: in the first case, where the phase shift angle is less than 120 degrees and in the second case, where the phase shift angle is more than 120 degrees. The outer switches of the circuit operate under ZVS condition and the inner switches operate under ZVZCS condition. It has been discovered that under ZCS condition of the inner switches, when the blocking capacitors decrease, they make the voltage across the blocking capacitor higher so the current reduce rapidly. A three-phase three-level DC-DC converter has a maximum efficiency of 93.5% when its load is of 5.7 kW. The results from the experiment have been compared to the results obtained by the MATLAB® simulator in order to confirm the validity of the proposed converter.
Some of the metrics are blocked by your
consent settings
Ripple current reduction using interleaving technique for three-level ZVZCS DC-DC converter
(2017-02-08)
Meesrisuk, Watanyu
;
Sarasiri, Nuapett
;
Jangwanitlert, Anuwat
This paper presents an output current ripple reduction technique for a three-level ZVZCS DC-DC converter which the output power is controlled by phase-shifted pulse width modulation (PSPWM). By means of 2 circuits of half bridge three-level DC-DC converter which operated by 90° phase difference or interleaving technique, as the results, the ripple of output current waveform is reduced significantly. The prototype of proposed circuit was designed and tested at 470 W of rated power, 310 V of input voltage, 0-48 V of output voltage and 50 kHz of switching frequency in order to compare the experimental results between interleaving and non-interleaving technique. It is found that the interleaving technique can reduce the ripple current on output current waveform for all phase-shifted angles. Finally, all switches in circuit can achieve soft-switching conditions and the maximum efficiency of converter is 93.7 %.
Some of the metrics are blocked by your
consent settings
A interleaved three-level half-bridge ZVZCS DC-DC converter using phase-shifted pulse-width modulation
(2016-01-05)
Meesrisuk, Watanyu
;
Jangwanitlert, Anuwat
This research paper presents an interleaved three-level half-bridge ZVZCS DC-DC converter by using the interleaved technique for reducing the ripple current of the proposed converter and using the dc blocking capacitor for achieving the soft switching condition. The outer switches of each cell can achieve the ZVS condition while the inner switches can operate under the ZCS condition. In addition, the voltage stress on devices (MOSFETs) equals to a half of input voltage because of using the three-level circuit. Finally, the operation modes and simulation results by PSIM software are illustrated in detail in order to confirm the validity of proposed concept.
Some of the metrics are blocked by your
consent settings
A novel Zero-Current-Switching of leading and lagging-leg switches for full-bridge phase-shifted PWM DC-DC converter
(2015-08-17)
Songboonkaew, J.
;
Jangwanitlert, A.
This paper presents a novel Zero-Current-Switching(ZCS) technique of the leading and lagging-leg switches. The leading-leg switches are achieved under ZCS by using an active auxiliary circuit and the lagging-leg switches are achieved under the ZCS by using a blocking capacitor voltage in primary side for decreasing the primary current. Moreover, the leading-lag switches are still achieved under the ZVS condition by using the energy of the leakage inductance. In this paper, the DC-DC full-bridge converter operation is described. Experimental results provided from a 1 kW 30 kHz prototype and validated the feasibility.
Some of the metrics are blocked by your
consent settings
Analysis of reset time for a novel three-phase three-level ZVZCS DC-DC converter using phase-shift PWM strategy
(2015-01-26)
Kongwirat, Thammachat
;
Jangwanitlert, Anuwat
The paper presents an analysis about the reset time of the primary current for a novel three-phase three-level ZVZCS DC-DC converter using phase-shift PWM strategy. The analysis shows the presence of the ZVS turn-on condition at outer switches of Branches A, B and C, ZVZCS turn-on and turn-off conditions at inner switches of the branches. For ZCS turn-off conditions at inner switches, DC blocking capacitors also affects resetting of the primary current directly and validates the consistency between simulation results using MATLABR and experimental results, which exhibits good agreement. The converter has maximum efficiency of 93.50% at 5.6 kW.
Some of the metrics are blocked by your
consent settings
Analysis of a wide load variation of ZVZCS phase-shifted PWM full-bridge DC-DC converter
(2014-10-15)
Jangwanitlert, A.
This paper presents a wide load variation of the improved ZVZCS phase-shifted PWM full-bridge dc-dc converter, which can deliver power efficiently. The key operation waveforms of the full-bridge converter from absolutely no-load to full-load conditions are described. In order to confirm wide load variations, the converter should not only operate with soft-switching from full load to no-load condition with satisfactory efficiency for the full range of operation, but the voltage across the output diode bridge also needs to be clamped to keep away from any reverse voltage overshoots arising during turn-off of the output rectifying diodes. In order to achieve zero-voltage switching (ZVS) at turn-on for all load conditions, the converter employs auxiliary coupled inductors near lossless auxiliary circuit. Moreover, the proposed topology is based on a current driven rectifier in order to clamp the voltage of the output rectifying diodes and also obtain ZVZCS of the converter operation, resulting in superior efficiency for all load conditions. In this paper, the converter operation is described. Experimental results provided from a 1 kW prototype validate the feasibility.
Some of the metrics are blocked by your
consent settings
An improved Three-Level Zero-Voltage and Zero-Current Switching PWM DC-DC converter for battery charger
(2014-01-01)
Jangwanitlert, A.
This paper describes a 2-kW Three-Level Zero-Voltage and Zero-Current Switching (TL-ZVZCS) PWM dc-dc converter for battery charger. To solve the disadvantages from TL-Zero-Voltage Switching (ZVS) such as a circulating primary current and parasitic voltage ringing on the dual diodes rectifier, a proposed simple auxiliary circuit is composed of a small capacitor with two small diodes is put on the transformer secondary side to achieve ZVZCS conditions of primary switches and to clamp secondary voltage rectifier. The auxiliary circuit does not give any losses in components and additional active switches, which provides the proposed circuit converter more effective and efficient. Moreover, this paper describes the key operation waveforms, operational modes and design considerations. The concept idea is verified by the MATLAB simulation. © 2014 IEEE.

KMITL

Browse

Filters

Settings

Sort By

Results per page

Search Results