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    ENHANCEMENT OF ARTIFICIAL IMMUNE SYSTEMS FOR THE TRAVELING SALESMAN PROBLEM THROUGH HYBRIDIZATION WITH NEIGHBORHOOD IMPROVEMENT AND PARAMETER FINE-TUNING
    (2024-01-01)
    Thapatsuwan, Peeraya
    ;
    Thapatsuwan, Warattapop
    ;
    Kulworatit, Chaichana
    This research investigates the enhancement of Artificial Immune Systems (AIS) for solving the Traveling Salesman Problem (TSP) through hybridization with Neighborhood Improvement (NI) and parameter fine-tuning. Two main experiments were conducted: Experiment A identified the optimal integration points for NI within AIS, revealing that position 2 (AIS+NIpos2) improved solution quality by an average of 27.78% compared to other positions. Experiment B benchmarked AIS performance with various enhancement techniques. Using symmetric and asymmetric TSP datasets, the results showed that integrating NI at strategic points and fine-tuning parameters boosted AIS performance by up to 46.27% in some cases. The hybrid and fine-tuned version of AIS (AIS-th) consistently provided the best solution quality, with up to a 50.36% improvement, though it required more computational time. These findings emphasize the importance of strategic combinations and fine-tuning for creating effective optimization algorithms.
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    Fine-tuning of wave-pipelines on FPGAs developed by the RTL design
    (2015-08-17)
    Sato, Tomoaki
    ;
    Chivapreecha, Sorawat
    ;
    Moungnoul, Phichet
    A wave-pipeline is a design technique for achieving high-speed and low-power operations also in field-programmable gate arrays (FPGAs). It realizes pipeline operations by adjusting delay times. Implementation of fine-tuning of wave-pipelines is possible to further increase the throughput. However, in the FPGA, it is not able to be executed by the restriction on the structure. This paper proposes a fine-tuning method for the FPGA developed by the register-transfer level (RTL) design. Although the RTL design of the FPGA has various advantages, it is required for a high-speed design for a routing delay which is larger than that of a conventional FPGA. The method is timing adjustment using a connection block with the RTL design. Results of analysis of the connection block show that the seven stages of the delay adjustment are possible in the block. In addition, the block can be used for rough-tuning of delay times. It is the area of less than half of the logic block.