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Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration
(2025-01-01)
Sato, Tomoaki
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Murakami, Anyu
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Chivapreecha, Sorawat
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Moungnoul, Phichet
This paper explores the evaluation and optimization of multi-bit input logic blocks (LBs) within RTL-designed FPGA architectures. Traditional FPGA designs face limitations in power consumption, delay, and area due to the constraints of reconfigurable circuits. The proposed architecture leverages RTL-level design capabilities to address these challenges and enables the co-design of FPGAs and ASICs. The authors evaluate the performance of 8-bit, 16-bit, and 32-bit input LBs in terms of delay, area, and synthesis feasibility. The results demonstrate that 8-bit input LBs achieve a delay of 0.68 ns with an area of 2202.48 μm<sup>2</sup>, outperforming multi-stage smaller LBs. Although 16-bit input LBs show potential for delay reduction, their synthesis demands significant time and results in a large area footprint, rendering them impractical. Synthesis of 32-bit input LBs was not feasible due to current tool limitations. These findings highlight the effectiveness of 8-bit input LBs for pattern matching tasks and emphasize the importance of application-specific optimization. The fixed routing feature of RTL-designed FPGAs facilitates the development of efficient, customizable designs tailored to specific workloads. This work contributes to the advancement of FPGA architectures, offering insights for future research on larger input LBs and their integration into high-performance applications.
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Application-Optimized FPGAs Design Using RTL-Designed FPGAs Architectures
(2025-01-01)
Sato, Tomoaki
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Murakami, Anyu
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Chivapreecha, Sorawat
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Moungnoul, Phichet
RTL-Designed Field-Programmable Gate Arrays (FPGAs) can describe FPGA functionality using Hardware Description Languages (HDLs), which means they can be easily customized to configure the FPGA. In conventional FPGAs, switches are used for routing control, making it impossible to design them using HDLs. This study leverages the customizable nature of RTL-Designed FPGAs to explore the optimal configuration of FPGAs for packet processing in computer networks. It demonstrates that a 4-input Look-Up Table (LUT) is superior to a 3-input LUT in terms of throughput and reveals that, as the number of LUT inputs increases, having 5 routing paths is more optimal than 4.
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Optimal Number of Wires for Circuits on RTLDesigned FPGAs
(2024-01-01)
Sato, Tomoaki
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Hayashihara, Yuya
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Yokota, Shione
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Chivapreecha, Sorawat
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Moungnoul, Phichet
FPGAs (Field-Programmable Gate Arrays) with reconfigurable features are used in various applications. However, circuits on FPGAs are inferior to circuits on ASICs in operating frequency, power consumption, and area. Co-design of FPGA and ASIC is one way to solve this problem. To realize this co-design, RTL-Designed FPGAs have been proposed by the authors. The features of the FPGAs are that they can be described only with HDL and that they can be realized with ordinary standard cells. Therefore, FPGAs and ASICs can be co-designed easily. Until now, the FPGAs have not been considered for optimal wiring count. In this paper, we clarify the optimum number of wires using a 4-bit adder circuit. In addition, cases in which more than that optimal number of wires is needed are discussed.
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0.5-V Mixed-Mode Universal Active Filter Using Multiple-Input OTAs
(2024-01-01)
Phatsornsiri, Punnavich
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Kumngern, Montree
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Nonthaputha, Thanat
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Asa, Ekachai
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Singsathien, Jateslid
This study introduces new 0.5 V, ultra-low power mixed-mode universal analog filter applying multiple-input operational transconductance amplifiers (MI-OTAs). The filter configuration based on MI-OTAs and two grounded capacitors to actualize a mixed-mode universal filter that can produce four modes second-order filters, that is low-pass, high-pass, band-pass, band-stop and all-pass filters, namely voltage-mode, current-mode, transimpedance mode, transconductance-mode, by appropriate selecting input signals. The filter's natural frequency can be electronically controlled. The mixed-mode filter was analyzed using CMOS 0.18μm process simulation from TSMC, operating with a 0.5 V power supply.
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Design QPSK Communication System by Software-Defined Radio (SDR)
(2023-01-01)
Tooprakai, Siraphop
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Kobthanyakit, Korpakit
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Suwanmad, Tin
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Moungnoul, Phichet
This paper presents the design of a QPSK communication system with Software-Defined Radio (SDR). SDR communication system is a system that uses software to control the digital signal processing (DSP) within a communication system, such as a mixer, filter, modulator and demodulator circuits, etc. This SDR communication system is flexible. and easy to update. Choose a hardware platform and software, which is USRP B210 and MATLAB, respectively. Design and test the QPSK communication system for both receiving and transmitting.
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Pilot Flight Data Processing System for Airline Management
(2023-01-01)
Moungnoul, Phichet
This paper presents the development of a pilot flight performance analysis system for airline management designed to show the performance of an aircraft. A system that brings flight data from aircraft then decode to find the relevant parameters. After that, the parameters were analyzed the results of the pilot's flight performance. The results to be displayed by showing the measurement tool then take the parameters obtained to display in a flight simulation. In order to display the event that needs to be monitored by the measurement tool. The flight response caused by the aircraft or operators themselves can be find flaws in the pilot's flight performance.
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Network Design for LTE-Pro
(2020-07-01)
Phangphan, Chanita
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A-Mapat, Narongchon
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Moungnoul, Phichet
This paper presents the design of the LTE-Pro network in the combination of LTE-LAA and LTE-LWA. By designing appropriate distance, density as a ratio and bandwidth allocation between 3 technologies in order to find the suitable cell location that enables the high throughput. From the variation between LWA (Wi-Fi Access point) or LAA (eNB) and Base Station (BS) to find Inter-Cell Interference Coordinate (ICIC) from the nearby BS via signal to interference plus Noise Ratio (SINR). The assumption that LAA node and LTE node had different radius, while LWA was randomly distributed between the distance D1 and D2, respectively. Then the ratio number of nodes and allocate frequencies bandwidth between 3 technologies. By using MATHLAB to simulate the operation of the LTE-Pro network. The results show that the design of the pico LTE-pro network with the range D1 is 3 : 4 of the LAA radius, and D2 is 4 : 5 of the LTE radius. The node ratio and the bandwidth allocation of LTE : LAA : LWA is 2 : 2 : 10 and 2 : 4 : 4 respectively are factors that affects the performance of LTE-Pro and will improve LTE-Pro network performance.
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Mitigation technique for LTE-LAA and LTE-LWA coexistence
(2020-07-01)
A-Mapat, Narongchon
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Moungnoul, Phichet
An implementation of Mobile network providers on 5G network are coexistence between LTE-LAA and LTE-LWA network. It was applied to achieve the objective of improve network performance and optimize resources. This paper is study the investigated LTE-LAA and LTE-LWA coexistence with Wi-Fi controlled Technique in different scenarios. The results show the distance between 50-600 meter and LTE-LWA was extremely affect by LTE-LAA. The controlled Wi-Fi AP technique is effective method to mitigate the network degradation problem.
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Impact of LTE-Pro on LTE-A Network
(2020-07-01)
A-Mapat, Narongchon
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Moungnoul, Phichet
This paper presents the design of LTE-Pro network performance in LTE-LAA and LTE-LWA interoperate scenarios. By offering data flow controlling technique, and modification between Time Division Duplex (TDD) and frequency division duplex (FDD) techniques on downlink sides. In order to find an optimal cell position that enables the data transmission in the communication channel or Throughput. From the variation of User Equipment (UE) and Node (eNB) or Base Station (BS) to find the Inter-Cell Interference Coordinate (ICIC) from other nearby BS via Signal to interference plus Noise Ratio (SINR). Assuming that the nodes of the LLA and LWA are distributed randomly, the distance is between 50-1, 200 meters. By using MATHLAB program to simulate the LTE-Pro network. The results showed that when the distance increased, the Throughput decreased in both cases and concluded that the 600 meters distance is the distance that affects the performance of LTE-Pro. And if the LTE-Pro network is to perform well, it must make the uplink and downlink Wi-Fi signal transmission to be FDD and TDD respectively.
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Throughtput investigated of coexistence Wi-Fi and LTE-U
(2019-11-01)
Moungnoul, Phichet
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A-Mapat, Narongchon
Implementation of the mobile network provider to improve the network performance and the resources optimization by implemented coexistence LTE-TDD, LTE-FDD network and Wi-Fi technology. The main interference is the adjacent cell interference (ACI) from coexisting network/technology, which affected to the network performance. This paper is investigated LTE/Wi-Fi technique in coexistence LTE-FDD/TDD. Results show the distance between 50-60 m and Wi-Fi access point should not over 12 given the best system. The throughput compared with normal case will describe in this paper.

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