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Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration
(2025-01-01)
Sato, Tomoaki
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Murakami, Anyu
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Chivapreecha, Sorawat
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Moungnoul, Phichet
This paper explores the evaluation and optimization of multi-bit input logic blocks (LBs) within RTL-designed FPGA architectures. Traditional FPGA designs face limitations in power consumption, delay, and area due to the constraints of reconfigurable circuits. The proposed architecture leverages RTL-level design capabilities to address these challenges and enables the co-design of FPGAs and ASICs. The authors evaluate the performance of 8-bit, 16-bit, and 32-bit input LBs in terms of delay, area, and synthesis feasibility. The results demonstrate that 8-bit input LBs achieve a delay of 0.68 ns with an area of 2202.48 μm<sup>2</sup>, outperforming multi-stage smaller LBs. Although 16-bit input LBs show potential for delay reduction, their synthesis demands significant time and results in a large area footprint, rendering them impractical. Synthesis of 32-bit input LBs was not feasible due to current tool limitations. These findings highlight the effectiveness of 8-bit input LBs for pattern matching tasks and emphasize the importance of application-specific optimization. The fixed routing feature of RTL-designed FPGAs facilitates the development of efficient, customizable designs tailored to specific workloads. This work contributes to the advancement of FPGA architectures, offering insights for future research on larger input LBs and their integration into high-performance applications.
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Application-Optimized FPGAs Design Using RTL-Designed FPGAs Architectures
(2025-01-01)
Sato, Tomoaki
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Murakami, Anyu
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Chivapreecha, Sorawat
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Moungnoul, Phichet
RTL-Designed Field-Programmable Gate Arrays (FPGAs) can describe FPGA functionality using Hardware Description Languages (HDLs), which means they can be easily customized to configure the FPGA. In conventional FPGAs, switches are used for routing control, making it impossible to design them using HDLs. This study leverages the customizable nature of RTL-Designed FPGAs to explore the optimal configuration of FPGAs for packet processing in computer networks. It demonstrates that a 4-input Look-Up Table (LUT) is superior to a 3-input LUT in terms of throughput and reveals that, as the number of LUT inputs increases, having 5 routing paths is more optimal than 4.
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Amplitude Stabilization of Frequency-Tunable Biquad Digital Oscillator Using Zero-Input Response Analysis
(2025-01-01)
Chivapreecha, Sorawat
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Suwannawach, Piyapan
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Sato, Tomoaki
This paper presents an analysis of the biquad digital oscillator, which leads to design improvements in the online oscillating frequency adjustment capabilities. The requirements for signal generation in a digital oscillator without input comprise the initial conditions as well as the coefficients, which are constants. The coefficient of biquad oscillator can be modified to be a tuning parameter for changing the oscillating frequency by the users. Although the frequency of the oscillating signal can be changed as desired, however, while the system is operating, the inconsistency of the changed coefficient with the initial conditions that emerge from the retained prior states causes the signal amplitude to lose its stability. The zero-input response of a system could be theoretically examined to identify and understand this behavior. Moreover, the issue of amplitude stabilization can be looked into and resolved with the use of the zero-input response analysis develop to an improvement, which results in maintaining the amplitude of the oscillating signal after the frequency change.
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Optimal Number of Wires for Circuits on RTLDesigned FPGAs
(2024-01-01)
Sato, Tomoaki
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Hayashihara, Yuya
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Yokota, Shione
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Chivapreecha, Sorawat
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Moungnoul, Phichet
FPGAs (Field-Programmable Gate Arrays) with reconfigurable features are used in various applications. However, circuits on FPGAs are inferior to circuits on ASICs in operating frequency, power consumption, and area. Co-design of FPGA and ASIC is one way to solve this problem. To realize this co-design, RTL-Designed FPGAs have been proposed by the authors. The features of the FPGAs are that they can be described only with HDL and that they can be realized with ordinary standard cells. Therefore, FPGAs and ASICs can be co-designed easily. Until now, the FPGAs have not been considered for optimal wiring count. In this paper, we clarify the optimum number of wires using a 4-bit adder circuit. In addition, cases in which more than that optimal number of wires is needed are discussed.
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Designing a Fine-Tuning Tool for Machine Learning with High-Speed and Low-Power Processing
(2018-12-24)
Sato, Tomoaki
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Chivapreecha, Sorawat
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Higuchi, Kohji
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Moungnoul, Phichet
Machine learning is used in various fields. In order to broaden its further applications, it is necessary to use an architecture that operates faster and with lower-power consumption than conventional architecture. In this paper, as an architecture for that, it is proposed to use the ASIC-FPGA architecture proposed by the authors. In circuits on FPGAS, wave-pipeline techniques can be introduced for further high through put processing. In order to further improve the performance of wave-pipelines on the FPGAS, fine-Tuning should be executed. A fine-Tuning tool essential for realizing these is developed.
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Comparison of frequency reuseschemes for LTE micro-macro cells
(2018-07-02)
Chaiwongkhan, Udornphan
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Sato, Tomoaki
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Matathong, Samakom
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Moungnoul, Phichet
LTE networks offer high capacity and high performance. Frequency Reuse schemes used in LTE network planning are optimized using inter-cell interference. Macro cells were install for large coverage area, but channel capacity is limited. Micro/macro technique used for increase capacity in the need high traffic area. The limiting factor the influences LTE performance is the interference from neighboring cells. This paper proposes FFR (Fraction Frequency Reuse) for micro/macro cells with sectoring. Micro/macro cells coordinated model is investigated. Simulation results to compare the capacity of micro/macro cell model cause of different number of carriers.
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A detection method of web authentication problems for mobile devices corresponding to IEEE 802.11ac
(2018-05-30)
Sato, Tomoaki
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Chivapreecha, Sorawat
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Higuchi, Kohji
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Moungnoul, Phichet
Improvement in the performance of mobile devices makes many opportunities to watch high resolution moving images using a public Wi-Fi LAN service. A web authentication may be required to specify the network user when accessing the public Wi-Fi LAN service. For some authentications, Google, Facebook and Twitter accounts are used. Although the use of these accounts provides convenience, it has serious problems. If the website for the authentication is a phishing site, the account may be abused. The reason is that it is difficult for many users to identify phishing sites. The identification using the CPU of a mobile device has a problem that it cannot deal with the throughput of IEEE 802.11ac. In this article, problems with web authentications used in public Wi-Fi LAN services are surveyed. Then, the authors propose a detection method of the problems that can deal with the throughput realized by IEEE 802.11ac and can process with low-power operations on mobile devices.
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Quality assessment of Thai rice kernels using low cost digital image processing system
(2018-05-30)
Kongsawat, Phuvin
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Chivapreecha, Sorawat
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Sato, Tomoaki
This paper presents a low cost digital image processing system for quality assessment of Thai rice kernels. Nowadays, Thailand is the top country which export rice into the world market, according to the mention of the Rice Trader, the export volume is 9,883,288 tons in 2016 and export value is 154,434 million baht or 4,401 million dollars. Thai rice quality is controlled by rice department, ministry of commerce Thailand in order to guarantee the quality in market including prices base on grade of rice quality. Thence, quality assessment of Thai rice kernels is required. Quality assessment or grading of Thai rice kernels usually use manual operation by person in cooperating with equipment called micrometer to measure geometrical features such as length, width, and area of rice kernels. This method takes a long time and also gives uncertainty in results due to eye fatigue because size of rice kernels is very small. Therefore, an image processing technique is then applied to measure size of Thai rice kernels. Proposed system consists of flatbed scanner and image processing algorithm which correspond to measure of Thai rice kernels. The low cost system for quality assessment of Thai rice kernels can be delivered to Thai rice industry, the certainty of results and speed of quality assessment can be significantly improved.
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Throughput of a Firewall Unit on FPGAS Developed by the RTL Design Methodology
(2017-10-19)
Sato, Tomoaki
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Chivapreecha, Sorawat
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Moungnoul, Phichet
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Higuchi, Kohji
The transmission speed of mobile communication systems for mobile and IoT (Internet of things) devices is getting faster. Advanced, high-speed and low-power processing on network packets are needed in these devices. To realize these performances in the devices, the authors have proposed FPGAS (field-programmable gate arrays) which are developed by the RTL (register-Transfer level) design methodology. As an application of the FPGAS for mobile communication systems, a firewall unit has been developed. However, the function of the firewall unit is only packet filtering. A function for deleting a packet passing through an unauthorized port has not been realized. In this paper, the authors design the firewall unit with the function of deleting the packet. The throughputs of the firewall unit are shown. Thus, it is clarified that high throughput can be accommodated.
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RCA on FPGAs designed by the RTL design methodology and wave-pipelined operation
(2016-09-06)
Sato, Tomoaki
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Chivapreecha, Sorawat
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Moungnoul, Phichet
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Higuchi, Kohji
Field-programmable gate arrays (FPGAs) are used in various systems that use reconfigurable function. Conventional FPGAs have been developed by a transistor-level description for minimizing routing delay. Although FPGAs developed by the register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the authors have advanced their development. They should be shown to operate in a practical throughput. For this purpose, circuits on them need to be designed and evaluated. In this paper, a ripple-carry adder (RCA) is designed on them and the throughput of the RCA is evaluated. The throughput shows that it is applicable to network processors. In addition, a wave-pipelined operation without changing the RCA reveals that the problem of routing delay in the FPGAs developed by the RTL methodology is mitigated.

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