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A Nanopower EEG Low-Pass Filter Using Current-Sharing Vertical Differential Pairs
(2025-01-01)
Pawarangkoon, Prajuab
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Ahmad, Rafidah
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Abdullah Zawawi, Ruhaifi
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Abd Manaf, Asrulnizam
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Surakampontorn, Wanlop
A follower-based g<inf>m</inf> - C low-pass filter that employs CMOS vertical source-couple-pair (VSCP) transconductors is proposed for practical use in EEG acquisition systems. The VSCP transconductor operates as a g<inf>m</inf> cell with current sharing and linearity enhancement features. It is applied in the first- and second-order g<inf>m</inf> - C sections cascaded to form a third-order low-pass filter targeting a 150-Hz bandwidth. To mitigate the effects of biasing current source mismatch, dynamic element matching (DEM) is optionally applied to the relevant biasing current source pairs, resulting in second harmonic distortion (HD2) and noise suppression. Implemented in a 0.18-µm process, the proposed filter consumes 16.3-nW power from a 1.2-V supply. Thanks to the DEM and VSCPs, the filter achieves a 150-mV<inf>P</inf> linear input range [measured at 1% total harmonic distortion (THD)], whereas the input-referred noise of 43 µV<inf>rms</inf> is obtained leading to a filter dynamic range (DR) of 65.15 dB. Overall performance comparisons with other recent nanopower filters indicate that the figure of merit (FoM) of this proposed filter is comparable, while the linear input range is larger.
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A 38.4 nW, 1.2 V, 250-Hz, 2nd-Order gm - C LPF With Degenerative SCP Transconductors Achieving 800-mVPP Input Range and 82.1- μVrms IRN for ECG Acquisition
(2025-01-01)
Thanapitak, Surachoke
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Pawarangkoon, Prajuab
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Surakampontorn, Wanlop
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Ahmad, Rafidah
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Abdullah Zawawi, Ruhaifi
In this brief, a 2{^{\text {nd} -order gm - C lowpass filter with a practical input linear range of 400mV P dedicated to ECG signal acquisition is proposed. This filter employs a degenerative source-coupled-pair circuit as a gm cell. It enhances the linear input range by a factor of × 4 compared with the source follower filter. Additionally, to mitigate the effect of current source mismatch, a dynamic element matching technique is applied. By doing so, HD2 is suppressed more than 1.5 dB over the entire passband frequency. This proposed filter is implemented in a 0.18 μ m CMOS process. It offers a 250-Hz bandwidth with input-referred noise and a dynamic range of 82.1 μ Vrms and 67.34 dB, respectively. The power consumption of 38.4 nW is achieved with a 1.2 V supply. Compared with other recent nano-power filters, the proposed filter provides the highest linear input range with competitive Figure-of-Merit to the top-tier designs. It is therefore beneficial to the practical implementation of a low-power ECG acquisition system.
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A Micropower Chopper CBIA Using DSL-Embedded Input Stage with 0.4 v EO Tolerance for Dry-Electrode Biopotential Recording
(2023-06-01)
Thanapitak, Surachoke
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Surakampontorn, Wanlop
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Sawigun, Chutham
A chopper instrumentation amplifier (IA) dedicated for bio-potential acquisition usually requires a linearized input stage for large electrode offset voltage accommodation. This linearization leads to excessive power consumption when sufficiently low input-referred noise (IRN) is required. We present a current-balance IA (CBIA) without the need for the input stage linearization. It uses two transistors to operate as an input transconductance stage and a dc-servo loop (DSL) at the same time. An off-chip capacitor completes the DSL by ac coupling the source terminals of the input transistors via chopping switches realizing a sub-Hz high-pass cutoff frequency for dc rejection. Fabricated in a 0.35-μm CMOS process, the proposed CBIA occupies 0.41 mm2 and consumes 1.19 μW from a 3 V dc supply. Measurements show that the IA achieves an input-referred noise of 0.91 μVrms over 100 Hz bandwidth. This corresponds to a noise efficiency factor of 2.22. Typical CMRR of 102.1 dB is achieved for zero offset and degraded to 85.9 dB when a ±0.3 V input offset was applied. Gain variation of 0.5% is maintained within the range of ±0.4 V input offset. The resulting performance meets well with the requirement for ECG and EEG recording using dry electrodes. A demonstration for the use of the proposed IA on a human subject is also provided.
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A 20-MHz 0.323-mW 23.9-dBm-IIP3 4th-order current-reuse lowpass filter
(2021-05-19)
Thanapitak, Surachoke
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Chulajata, Tatcha
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Sedtheetorn, Pongsatorn
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Hayatleh, Khaled
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Surakampontorn, Wanlop
A source follower lowpass filter which has a capability of bulk-attenuation cancellation in higher order is presented. Under strong inversion bias arrangement for high frequency application, this fourth-order-filter is simulated in a 0.18 μm standard CMOS process and exhibits a 20 MHz bandwidth with total power consumption of 0.323 mW from 1.8 V supply. Third order intermodulation distortion verification with 1.9 and 2.1 MHz signal archives 23.9 dBm IIP3 with 75.5 dB dynamic range. By using figure-of-merit as a benchmark indicator, the proposed filter is one of the top in its class with the lowest power consumption.
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Dual-Output CMOS Voltage Squarer Circuit
(2020-06-01)
Boonchu, Boonchai
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Surakampontorn, Wanlop
A dual-output CMOS voltage squarer circuit has been proposed. The proposed circuit structure is based on the current squarer circuit core. The differential output OTA which is the combination of class-AB amplifier and is employed as current-to-voltage units in order to provide the squarer output in voltage form. The performances of the proposed squarer have been confirmed by circuit simulation employing 0.25 μm CMOS technology. Simulation results show that the circuit performs the squaring function under ±1.5 V power supply voltage and the static power consumption is less than 1.2 mW.
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Messages from General chair
(2019-11-01)
Surakampontorn, Wanlop
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Message from General Chair
(2019-11-01)
Surakampontorn, Wanlop
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Low-voltage diode-R current squarer circuit
(2019-03-01)
Boonchu, Boonchai
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Surakampontorn, Wanlop
In this paper, a Diode-R squaring circuit cell is presented. It is then employed to realize a new current squarer circuit that suitable for implemented in BJT technology. The design configuration is through the combination of a simple current mirror and a current inverter circuit. The proposed current squarer can operate for input current of ±19 μA, with the harmonic distortion of about 1.886%. Furthermore, its features low voltage of 1.5 V single power supply and 0.42 mW power consumption. The SPICE simulation results are used to confirm the performance of the circuit and the validity of the design technique.
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Voltage Differencing Gain Amplifier-Based Quadrature Oscillator Employing All Grounded Passive Elements
(2018-12-24)
Satansup, Jetsdaporn
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Tangsrirat, Worapong
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Surakampontorn, Wanlop
This article deals with the configuration of an electronically tunable quadrature oscillator using voltage differencing gain amplifiers (VDGAs) as active devices. The circuit employs a single grounded resistor and two grounded capacitors, which is advantageous from the monolithic integration point of view. It serves as an alternative application of VDGA device and provides the advantages of availability of two quadrature output voltages, independent control of oscillation condition and oscillation frequency by electronic means through the external biasing currents, and good various sensitivity performances. The results from PSPICE simulation program are included that demonstrate the working of the proposed circuit.
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A novel current-mode temperature-insensitive APF using a single CCCII+2 with grounded capacitor
(2016-01-01)
Kaewdang, Khanittha
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Kumwachara, Kiattisak
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Surakampontorn, Wanlop
A novel first-order all-pass filter (APF) using a single positive second-generation current conveyor of current gain equal to 2 (named as CCII+2), one grounded capacitor and one resistor is proposed. From the proposed CCII+2 based filter, by replacing the CCII+2 and the resistor with a positive second-generation current-controlled conveyor of current gain equal to 2 (named as CCCII+2), a new filter which requires only a single CCCII+2 and one grounded capacitor is achieved. In order to operate in current-mode with temperature insensitive, a temperature compensation technique for the CCCII is also proposed. The experimental and PSPICE simulation results found in a good agreement with theoretical analysis are included.

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