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    Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration
    (2025-01-01)
    Sato, Tomoaki
    ;
    Murakami, Anyu
    ;
    Chivapreecha, Sorawat
    ;
    Moungnoul, Phichet
    This paper explores the evaluation and optimization of multi-bit input logic blocks (LBs) within RTL-designed FPGA architectures. Traditional FPGA designs face limitations in power consumption, delay, and area due to the constraints of reconfigurable circuits. The proposed architecture leverages RTL-level design capabilities to address these challenges and enables the co-design of FPGAs and ASICs. The authors evaluate the performance of 8-bit, 16-bit, and 32-bit input LBs in terms of delay, area, and synthesis feasibility. The results demonstrate that 8-bit input LBs achieve a delay of 0.68 ns with an area of 2202.48 μm<sup>2</sup>, outperforming multi-stage smaller LBs. Although 16-bit input LBs show potential for delay reduction, their synthesis demands significant time and results in a large area footprint, rendering them impractical. Synthesis of 32-bit input LBs was not feasible due to current tool limitations. These findings highlight the effectiveness of 8-bit input LBs for pattern matching tasks and emphasize the importance of application-specific optimization. The fixed routing feature of RTL-designed FPGAs facilitates the development of efficient, customizable designs tailored to specific workloads. This work contributes to the advancement of FPGA architectures, offering insights for future research on larger input LBs and their integration into high-performance applications.
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    Optimal Number of Wires for Circuits on RTLDesigned FPGAs
    (2024-01-01)
    Sato, Tomoaki
    ;
    Hayashihara, Yuya
    ;
    Yokota, Shione
    ;
    Chivapreecha, Sorawat
    ;
    Moungnoul, Phichet
    FPGAs (Field-Programmable Gate Arrays) with reconfigurable features are used in various applications. However, circuits on FPGAs are inferior to circuits on ASICs in operating frequency, power consumption, and area. Co-design of FPGA and ASIC is one way to solve this problem. To realize this co-design, RTL-Designed FPGAs have been proposed by the authors. The features of the FPGAs are that they can be described only with HDL and that they can be realized with ordinary standard cells. Therefore, FPGAs and ASICs can be co-designed easily. Until now, the FPGAs have not been considered for optimal wiring count. In this paper, we clarify the optimum number of wires using a 4-bit adder circuit. In addition, cases in which more than that optimal number of wires is needed are discussed.
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    Short range electromagnetic interface using 0.35 μm CMOS blocks for temperature monitoring in isolated areas
    (2022-11-01)
    Sotner, Roman
    ;
    Jerabek, Jan
    ;
    Polak, Ladislav
    ;
    Prokop, Roman
    ;
    Ayten, Umut Engin
    Introduction: Infra-red (IR) and visible light (VL) based systems developed for transmission of information about physical quantities (e.g. humidity, temperature) out from closed areas, cannot be effectively employed in case of specific conditions in a targeted environment (because of fog or vapor for example). Objectives: In this work, we introduce a concept of wireless short-range transmitter and receiver to sense physical quantities, for instance temperature, with slow variation. The proposed concept is able to transmit analog-based information from isolated environments (e.g. aquariums or environments for plant growing) with high immunity against vapor and fog that limits standard optical (laser, IR band) methods of communication. Methods: In this work, a new concept of short range radiofrequency (RF) communication device consisting of transmitting and receiving parts build from active devices fabricated in 0.35 μm I3T25 3.3 V CMOS process and ferrite antennas is selected. RF part uses medium-wave propagation within 10 mm distance at frequency 700 kHz. Such an approach offers minimal path loss of the radiated energy of a signal and low-gain amplification required for restoration of similar levels as available at the transmitting side. Results: The processing of base-band signals of simple (sine wave) and complex (electrocardiogram) character was verified experimentally through the system. Application example of temperature monitoring in a closed environment, based on a temperature sensor (thermistor), verifies operationability in temperature range from 10 °C up to 50 °C. Conclusion: Compared to state-of-the-art solution, the presented concept has several advantages, for instance: less complexity; using of simpler type of modulation and demodulation; lower power consumption and significantly reduced issues caused by an environment with special transmission conditions (e.g. fog and vapor). The obtained results are in good agreement with expectations. Among others, the presented system brings beneficial performances for similar applications targeting on monitoring of low-frequency or slowly varying signals.
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    A programmable artificial neural network coprocessor for handwritten digit recognition
    (2019-07-01)
    Wisayataksin, Sumek
    ;
    Boonyuu, Geranun
    This paper proposes the hardware architecture of an artificial neural network coprocessor that its structure can be programmable. The number of neurons in each layer of a feedforward network can be set by writing configuration registers. The processing unit with four MACs and the sigmoid calculation engine are connected in eight pipeline stages to enhance the processing speed. The application of handwritten digit recognition from the MNIST database was performed to verify the performance of proposed architecture. The design was developed with Verilog HDL and implemented on the Xilinx Artix-7 XC7A35T FPGA. The experimental results revealed that the speed of back-propagation learning and validation process can be up to 47 times faster than computation on ARM Cortex-A4 CPU, while the recognition rate is still the same.
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    An FPGA architecture for ASIC-FPGA co-design to streamline processing of IDSs
    (2016-01-01)
    Sato, Tomoaki
    ;
    Chivapreecha, Sorawat
    ;
    Moungnoul, Phichet
    ;
    Higuchi, Kohji
    Novel methods for unauthorized access are always made. For cyber security measures in mobile devices, low-power and high-speed processing is very important. Despite these situations, a CPU for mobile devices is a very low processing capacity in order to focus on low-power operations and does not have sufficient performance for processing detection processing for unauthorized access. In contrast, a field-programmable gate array (FPGA) can apply to cyber security processing on mobile devices. By using the FPGA, cyber security processing is able to use parallel processing, super pipeline and processing that is independent of a word width size. However, the FPGA has a problem that the delay times of arithmetic circuits are longer than that of an application specific integrated circuit (ASIC) or CPU. In this paper, the authors propose an FPGA architecture for ASIC-FPGA co-design for addressing the problem. In order to evaluate the architecture, adders are enhanced by ASIC-FPGA co-design and evaluated. As a result, it is shown that the problem with the delay times of arithmetic circuits is solved.