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Two CMOS Wilkinson Power Dividers Using High Slow-Wave and Low-Loss Transmission Lines
(2024-08-01)
Pakasiri, Chatrpol
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Teng, Wei Sen
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Wang, Sen
This work presents two Wilkinson power dividers (WPDs) using multi-layer pseudo coplanar waveguide (PCPW) structures. The PCPW-based WPDs were designed, implemented, and verified in a standard 180 nm CMOS process. The proposed PCPW features high slow-wave and low-loss performances compared to other common transmission lines. The two WPDs are based on the same PCPW structure parameters in terms of line width, spacing, and used metal layers. One WPD was realized in a straight PCPW-based layout, and the other WPD was realized in a meandered PCPW-based layout. Both the two WPDs worked up to V-band frequencies, as expected, which also demonstrates that the PCPW guiding structure is less susceptible to the effects of meanderings on the propagation constant and characteristic impedance. The meandered design shows that the measured insertion losses were about 5.1 dB, and its return losses were better than 17.5 dB at 60 GHz. In addition, its isolation, amplitude imbalance, and phase imbalance were 18.5 dB, 0.03 dB, and 0.4°, respectively. The core area was merely 0.2 mm × 0.23 mm, or 1.8 × 10−3λ<inf>o</inf>2.
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Electronically tunable compact inductance simulator with experimental verification
(2024-06-01)
Bhardwaj, Kapil
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Srivastava, Mayank
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Kumar, Anand
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Singh, Ramendra
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Tangsrirat, Worapong
A novel inductance simulation circuit employing only two dual-output voltage-differencing buffered amplifiers (DO-VDBAs) and a single capacitance (grounded) is proposed in this paper. The reported configuration is a purely resistor-less realization that provides electronically controllable realized inductance through biasing quantities of DO-VDBAs and does not rely on any constraints related to matched values of parameters. This structure exhibits excellent behavior under the influence of tracking errors in DO-VDBAs and does not exhibit instability at high frequencies. The simple and compact metal-oxide semiconductor (MOS) implementation of the DO-VDBAs (eight MOS per DO-VDBA) and adoption of grounded capacitance make the proposed circuit suitable for on-chip realization from the perspective of chip area consumption. The function of the pure grounded inductance is validated through high pass/bandpass filtering applications. To test the proposed design, simulations were performed in the PSPICE environment. Experimental validation was also conducted using the integrated circuit CA3080 and operational amplifier LF-356.
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A Compact 0.73~3.1 GHz CMOS VCO Based on Active-Inductor and Active-Resistor Topology
(2024-06-01)
Pakasiri, Chatrpol
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Hsu, Ke Chung
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Wang, Sen
In this paper, a wideband VCO that covers popular Long-Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz frequencies is designed and developed in a standard 0.18 μm CMOS process. The VCO utilizes active inductors to achieve coarse-tuning of the inductance and a compact chip area. Moreover, an active feedback resistor is introduced into the active inductor for fine-tuning of the inductance. The feedback resistor also affects the equivalent resistance of the active inductor; therefore, wide inductance tuning and low power consumption can be obtained by optimizing the resistor. The core area of the fabricated CMOS chip is merely 0.046 mm2, excluding all testing pads. With a 6.7~10.1 mW DC consumption, the measured oscillation frequencies range from 0.73 GHz to 3.1 GHz, which demonstrates a 123.8% tuning range. At the frequencies of interest, the measured phase noises are from −80.7 to −84.5 dBc/Hz at a 1 MHz offset frequency.
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Cost-Effective Near Infrared Fluorescence Wide-Field Camera for Breast Tumor Imaging
(2023-08-01)
Juhong, Aniwat
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Li, Bo
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Yao, Cheng You
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Yang, Chia Wei
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Liu, Kunli
Near-infrared (NIR) fluorescence imaging has long been proven useful for numerous medical applications, especially image-guided surgery since it can deeply penetrate tissue and acquire a fluorescence image from the FDA-approved fluorescence dye known as indocyanine green (ICG). NIR imaging-guided surgery can help enhance outcomes by better defining surgical margins and minimizing operative time. However, most commercial NIR fluorescence imaging systems are bulky and expensive. In this work, we introduce a low-cost and portable NIR fluorescence imaging system. The proposed system exploits an inexpensive complementary metal-oxide-semiconductor (CMOS) based on Nyxel® technology, considerably improving quantum efficiency (QE) in the NIR range. Therefore, it can acquire a NIR fluorescence image with outstanding quality. Furthermore, we conjugated ICG with nanoworm particles (NWs-ICG) since nanoparticle-conjugated dye can increase accumulation in a tumor. We show impressive applications of our system for ex vivo tissues and in vivo image-guided surgery using NWs-ICG as a contrast agent for breast tumors from transgenic mice.
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A 10 GHz Compact Balun with Common Inductor on CMOS Process
(2023-01-01)
Pakasiri, Chatrpol
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Xu, Jian Long
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Wang, Sen
This paper presents a compact balun with a common inductor design. The design used Wilkinson-type balun topology with modified lumped transmission lines and a common inductor to realize circuit size reduction on a lossy CMOS process. Measurements of the prototype chip had a reflection coefficient below 17.8 dB at all ports, an insertion loss of 1.98 dB, and an isolation of 16.8 dB. The chip size was only 0.025λ<inf>0</inf> × 0.034λ<inf>0</inf>.
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New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation
(2023-01-01)
Kumar, Prashant
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Srivastava, Pushkar
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Ranjan, Rajeev Kumar
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Kumngern, Montree
We present here a simple three P-type MOSFET-based grounded memristor emulator model. The model is designed to achieve zero static power dissipation and is done so by eliminating the external DC supply i.e., no DC bias. The proposed memristor emulator model has extremely low dynamic power dissipation as well which comes to around 175 nW i.e., ∼ 67% improvement compared to recent work. A mathematical analysis is carried out to present the relevance of this design. Simulations were done on Cadence Virtuoso 90 nm technology node and fingerprints of the proposed memristor emulator were obtained. The layout area occupied by the model is approx 1154.69 μ m2 and an external capacitor is connected to add tunability to the circuit. Furthermore, Monte Carlo and corner analysis validate the robust nature of the design. Besides, simulations have been experimentally verified using CD-4007 CMOS integrated circuit (IC) to make the design practically feasible. Furthermore, the design offers advantages such as extremely less overall power consumption and smaller chip area that could possibly pave the path for fabrication using standard CMOS technologies. At last, an application of the proposed model depicting in-memory computation through a memristor emulator crossbar array is presented in brief.
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A compact floating and grounded memristor model using single active element
(2022-12-01)
Prasad, Sagar Surendra
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Kumar, Prashant
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Raj, Niranjan
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Sharma, Pankaj Kumar
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Priyadarshini, Bindu
Memristor with defined operational specifications is a challenging task that promotes innovation in emulation circuit modelling. This article presents a single active block based compact memristor emulator architecture which is suitable for both floating and grounded circuit topologies. It effectively operates in incremental/decremental modes in both the configurations. The proposed model utilizes only one Differential Voltage Current Conveyor Transconductance Amplifier (DVCCTA) as an active block along with a few passive components. It discourages the use of extra sub-circuit components like multiple active blocks, summers and multipliers. The circuit is intended to work at ±1 V of dc power supply and has a power consumption of 8.74 mW. The proposed emulator model exhibits all the characteristics of an ideal memristor with an operating frequency of 12.8 MHz. It has wide working voltage range of 50–500 mV. The memristor model is built and simulated using the TSMC 0.18 μm CMOS process parameter. The reliability and effectiveness of the proposed model is verified through non-ideal, Monte-Carlo, process corner, non-volatility and temperature variation analysis. Furthermore, the memristor prototype is constructed on the breadboard using discrete ICs AD844AN and CA3080. The experimental outcome is found in accordance with the simulation. The applicability of the proposed memristor model is verified by implementing a memristor based Schmitt trigger circuit.
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Short range electromagnetic interface using 0.35 μm CMOS blocks for temperature monitoring in isolated areas
(2022-11-01)
Sotner, Roman
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Jerabek, Jan
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Polak, Ladislav
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Prokop, Roman
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Ayten, Umut Engin
Introduction: Infra-red (IR) and visible light (VL) based systems developed for transmission of information about physical quantities (e.g. humidity, temperature) out from closed areas, cannot be effectively employed in case of specific conditions in a targeted environment (because of fog or vapor for example). Objectives: In this work, we introduce a concept of wireless short-range transmitter and receiver to sense physical quantities, for instance temperature, with slow variation. The proposed concept is able to transmit analog-based information from isolated environments (e.g. aquariums or environments for plant growing) with high immunity against vapor and fog that limits standard optical (laser, IR band) methods of communication. Methods: In this work, a new concept of short range radiofrequency (RF) communication device consisting of transmitting and receiving parts build from active devices fabricated in 0.35 μm I3T25 3.3 V CMOS process and ferrite antennas is selected. RF part uses medium-wave propagation within 10 mm distance at frequency 700 kHz. Such an approach offers minimal path loss of the radiated energy of a signal and low-gain amplification required for restoration of similar levels as available at the transmitting side. Results: The processing of base-band signals of simple (sine wave) and complex (electrocardiogram) character was verified experimentally through the system. Application example of temperature monitoring in a closed environment, based on a temperature sensor (thermistor), verifies operationability in temperature range from 10 °C up to 50 °C. Conclusion: Compared to state-of-the-art solution, the presented concept has several advantages, for instance: less complexity; using of simpler type of modulation and demodulation; lower power consumption and significantly reduced issues caused by an environment with special transmission conditions (e.g. fog and vapor). The obtained results are in good agreement with expectations. Among others, the presented system brings beneficial performances for similar applications targeting on monitoring of low-frequency or slowly varying signals.
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A low-phase-noise and low-power CMOS colpitts VCO using Gm boosting and capacitance switching techniques
(2021-01-01)
Pakasiri, Chatrpol
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You, Jia Hao
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Wang, Sen
This letter presents a low-power and low-phase-noise 5-GHz VCO fabricated in a standard CMOS 0.18-μm process. The low power dissipation was achieved by using the PMOS cross-coupled pair and G<inf>m</inf>-boosting topology, and the low phase noise was obtained by adding two pairs of switched capacitor array. The VCO consumed a dc power of 2.92 mW with the supply voltage of 1 V. The measured phase noises were − 104.6 dBc/Hz and − 117.4 dBc/Hz at 1 MHz offset frequency with switched off and on capacitances, respectively, which demonstrated 12.8-dB improvement.
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A Single Parameter Voltage Adjustable Immittance Topology for Integer- And Fractional-Order Design Using Modular Active CMOS Devices
(2021-01-01)
Sotner, Roman
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Jerabek, Jan
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Polak, Ladislav
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Prokop, Roman
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Jaikla, Winai
A simple single parameter adjustable immittance concept designed with modular active devices, fabricated in I3T $25~0.35~\mu \text{m}$ 3.3 V CMOS process of ON Semiconductor, is introduced. The proposed devices employ an integer-order capacitor and specifically designed fractional-order capacitors (sometimes called constant phase elements). The proposed active topology consists of two simple active elements, namely a linearly voltage adjustable operational transconductance amplifier and a voltage differencing unity gain voltage follower/buffer, and only two passive elements, i.e. redundancy is minimized. The designed topology offers generation of an adjustable immittance having both the capacitive and inductive character. The importance of the order as well as the value of the pseudo-capacitance for design and analyzes are shown, including all important parasitic features for estimation of expected operational bandwidth which have to be considered in the design. The operational bandwidth is determined by high values of approximants of fractional-order capacities (225, 56 and $8.8~\mu \text{F}$ /seĉ1- $\alpha $ , where $\alpha $ represents the order equal to 0.25, 0.5 and 0.75, respectively). These parameters result into ranges between tens of Hz and units-tens of kHz. The adjustability of the transconductance from 70 to $700~\mu \text{S}$ by the driving voltage between 0.05 and 0.5 V offers approximately one decade change of equivalent capacitance and inductance. Laboratory-based experiments done with a fabricated prototype confirmed the theoretical presumptions.

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