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Author: search.filters.author.Austin, AnuSubject: search.filters.subject.MEMS capacitive microphone

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    Fabrication of Contour Cavity Using Multi-Exposure Lithography for MEMS Capacitive Microphone
    (2018-07-02)
    Jantawong, Jirawat
    ;
    Atthi, Nithi
    ;
    Leepattarapongpan, Chana
    ;
    Jeamsaksiri, Wutthinan
    ;
    Austin, Anu
    This paper presents a novel technique to optimize a capacitive pressure sensor with multi-exposure dose lithography. As part of achieving high signal to noise ratio (SNR) in microphone, a new design was implemented. The new design defies the conventional wisdom of parallel plate theory and implement a concept of contour cavity (backplate) to follows the diaphragm deflection. This 3-dimensional contour cavity (CC) is fabricated by multi-exposure dose lithography with single silicon etching process. The CC structure with different etched depth of 0.65, 1.15, and 1.57 micron were fabricated by multi-exposure dose of 92, 120, and 210 mJ/cm<sup>2</sup>on 5.0 micron thick photoresist and single step etching with CF<inf>4</inf>/O<inf>2</inf>plasma (Si/PR etch selectivity: 1.3). Due to this novel contour cavity design, polysilicon membrane with 0.8 micron thick and a diameter of 930 micron structure produces the capacitance value of 2.88 pF, which is 28.6% higher than that of conventional parallel plate capacitive sensor.
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    Effects of Annealing Process on the Electrical Properties of MEMS Capacitive Microphone
    (2018-07-02)
    Jantawong, Jirawat
    ;
    Leepattarapongpan, Chana
    ;
    Chaowicharat, Ekalak
    ;
    Jeamsaksiri, Wutthinan
    ;
    Austin, Anu
    In this paper, the effects of annealing temperature after pre-bonding device wafer and cover wafer during wafer fusion bonding process on the electrical properties of MEMS-based capacitive microphone with 0.53 μm thick poly-Si membrane were investigated. By the annealing in N2 ambient (14 SLM) at 900°C for 30 min, the device exhibited capacitance of 2.0 pF with pull-in voltage of 12 V. The significantly improvement of electrical properties is related to the reducing of residual stress in poly-Si membrane to near-zero level by using suitable annealing condition.