This paper proposes the hardware architecture of an artificial neural network coprocessor that its structure can be programmable. The number of neurons in each layer of a feedforward network can be set by writing configuration registers. The processing unit with four MACs and the sigmoid calculation engine are connected in eight pipeline stages to enhance the processing speed. The application of handwritten digit recognition from the MNIST database was performed to verify the performance of proposed architecture. The design was developed with Verilog HDL and implemented on the Xilinx Artix-7 XC7A35T FPGA. The experimental results revealed that the speed of back-propagation learning and validation process can be up to 47 times faster than computation on ARM Cortex-A4 CPU, while the recognition rate is still the same.
