KMITL

Permanent URI for this communityhttps://dspace.kmitl.ac.th/handle/123456789/1

Browse

Search Results

Now showing 1 - 10 of 16

Some of the metrics are blocked by your
consent settings
Continuously Tunable Frequency and Phase Biquad Oscillator
(2026-05-01)
Chivapreecha, Sorawat
;
Suwannawach, Piyapan
This paper presents an improvement to the performance of a biquad oscillator, which is a recursive oscillator known for its excellent long-term stability. However, a significant limitation is that the oscillation frequency cannot be changed while the system is operating. Directly changing the frequency during operation causes the amplitude of the generated signal to vary significantly, either increasing or decreasing. A zero-input response analysis is used to understand the cause of this problem and to develop a solution that allows the amplitude of the generated signal to remain constant even when the oscillation frequency is changed during operation. In addition, this paper presents a method for controlling the phase of the generated signal by using a 1st-order IIR phase shifter structure. The proposed structure is specifically designed to allow the phase of the signal at the oscillation frequency to be adjusted continuously and independently of the frequency parameter. This integrated oscillator enables real-time, independent control of both signal frequency and phase without amplitude drift, making it suitable for applications requiring precise and dynamic signal synthesis.
Some of the metrics are blocked by your
consent settings
Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration
(2025-01-01)
Sato, Tomoaki
;
Murakami, Anyu
;
Chivapreecha, Sorawat
;
Moungnoul, Phichet
This paper explores the evaluation and optimization of multi-bit input logic blocks (LBs) within RTL-designed FPGA architectures. Traditional FPGA designs face limitations in power consumption, delay, and area due to the constraints of reconfigurable circuits. The proposed architecture leverages RTL-level design capabilities to address these challenges and enables the co-design of FPGAs and ASICs. The authors evaluate the performance of 8-bit, 16-bit, and 32-bit input LBs in terms of delay, area, and synthesis feasibility. The results demonstrate that 8-bit input LBs achieve a delay of 0.68 ns with an area of 2202.48 μm<sup>2</sup>, outperforming multi-stage smaller LBs. Although 16-bit input LBs show potential for delay reduction, their synthesis demands significant time and results in a large area footprint, rendering them impractical. Synthesis of 32-bit input LBs was not feasible due to current tool limitations. These findings highlight the effectiveness of 8-bit input LBs for pattern matching tasks and emphasize the importance of application-specific optimization. The fixed routing feature of RTL-designed FPGAs facilitates the development of efficient, customizable designs tailored to specific workloads. This work contributes to the advancement of FPGA architectures, offering insights for future research on larger input LBs and their integration into high-performance applications.
Some of the metrics are blocked by your
consent settings
Application-Optimized FPGAs Design Using RTL-Designed FPGAs Architectures
(2025-01-01)
Sato, Tomoaki
;
Murakami, Anyu
;
Chivapreecha, Sorawat
;
Moungnoul, Phichet
RTL-Designed Field-Programmable Gate Arrays (FPGAs) can describe FPGA functionality using Hardware Description Languages (HDLs), which means they can be easily customized to configure the FPGA. In conventional FPGAs, switches are used for routing control, making it impossible to design them using HDLs. This study leverages the customizable nature of RTL-Designed FPGAs to explore the optimal configuration of FPGAs for packet processing in computer networks. It demonstrates that a 4-input Look-Up Table (LUT) is superior to a 3-input LUT in terms of throughput and reveals that, as the number of LUT inputs increases, having 5 routing paths is more optimal than 4.
Some of the metrics are blocked by your
consent settings
Amplitude Stabilization of Frequency-Tunable Biquad Digital Oscillator Using Zero-Input Response Analysis
(2025-01-01)
Chivapreecha, Sorawat
;
Suwannawach, Piyapan
;
Sato, Tomoaki
This paper presents an analysis of the biquad digital oscillator, which leads to design improvements in the online oscillating frequency adjustment capabilities. The requirements for signal generation in a digital oscillator without input comprise the initial conditions as well as the coefficients, which are constants. The coefficient of biquad oscillator can be modified to be a tuning parameter for changing the oscillating frequency by the users. Although the frequency of the oscillating signal can be changed as desired, however, while the system is operating, the inconsistency of the changed coefficient with the initial conditions that emerge from the retained prior states causes the signal amplitude to lose its stability. The zero-input response of a system could be theoretically examined to identify and understand this behavior. Moreover, the issue of amplitude stabilization can be looked into and resolved with the use of the zero-input response analysis develop to an improvement, which results in maintaining the amplitude of the oscillating signal after the frequency change.
Some of the metrics are blocked by your
consent settings
Embedded Hardware Implementation of Noise Gate on STM32 Processor Using MATLAB/Simulink
(2025-01-01)
Jongsataporn, Thitaphan
;
Chivapreecha, Sorawat
This paper presents a model-based approach for developing a digital signal processing (DSP) system, specifically focusing on a Noise Gate application, using MATLAB/Simulink, and deploying it on the STM32F769I-Discovery board. The study thoroughly examines the advantages of model-based hardware implementation, particularly in facilitating rapid prototyping for real-time applications in educational contexts. The STM32F769I is powered by a high-performance Arm® Cortex®-M7 core, which can execute DSP instructions efficiently. Its ample memory and built-in debugging tools enhance its suitability for complex signal processing tasks. The implementation leverages MATLAB/Simulink and its robust compatibility with the STM32 hardware, allowing for seamless software and hardware component integration. The powerful model-based development features streamline the transition from simulation to physical hardware, reducing development time and enhancing reliability. The Noise Gate application is designed to control audio signals effectively, eliminating unwanted background noise through user-defined parameters such as threshold, attack time, and release time, which optimize performance based on specific audio environments. Additionally, the design applies a first-order IIR low-pass as a smoothing filter, which dynamically adjusts the gain according to the characteristics of the incoming audio signal. This ensures gradual opening and closing of the gate, resulting in smoother audio transitions. The results demonstrate significant noise suppression and overall audio quality enhancement, highlighting the practicality of employing model-based design methodologies for DSP applications. Furthermore, the insights gained from this study contribute to efficient hardware prototype development and offer implications for future projects in the field of digital signal processing.
Some of the metrics are blocked by your
consent settings
Linear Phase FIR Filter Design for Digital Hearing Aids Using a Neural Network-Based Optimization
(2024-01-01)
Chivapreecha, Sorawat
;
Yospanya, Poonna
A neural network-based optimization for the design of linear phase digital filters used in digital hearing aid applications is presented in this paper. To achieve hearing loss compensation, a 53-tap finite impulse response (FIR) filter is utilized, and the weights of the trained network can be used to obtain the impulse response of the FIR filter. The target frequency response or label comes from the audiogram, the training data is created, and a linear perceptron supervised learning model is used. Audiogram matchings are shown in design examples. The proposed neural network-based design approach can give a very high accuracy, high processing speed when compared with the existing methods, and also low complexity in filter structure realization.
Some of the metrics are blocked by your
consent settings
Tunable 1st Order IIR Phase Shifter Design and Implementation
(2024-01-01)
Chivapreecha, Sorawat
;
Jongsataporn, Thitaphan
This paper presents a new phase shifter which is a first-order infinite impulse response (IIR) filter that can shift phase both in phase-lead (0° to+180°) and phase-lag (-180° to 0°) fashion. Moreover, continuous phase tuning is also proposed in our phase shifter. The z-transform pair of phase-shifted cosine signal is utilized as the origin, then factorization of such term can give transfer function of first-order IIR phase shifter. The filter structure realization of the tunable phase shifter will be shown and applied with a digital cosine oscillator. Both simulation and hardware experiments can show phase-shifted signals in real-time controlled by phase-tuning parameters compared with a cosine reference signal as a demonstration. The allpass phase shifter will be used as a benchmark, and trade-off analysis using the proposed phase shifter will also be discussed.
Some of the metrics are blocked by your
consent settings
Optimal Number of Wires for Circuits on RTLDesigned FPGAs
(2024-01-01)
Sato, Tomoaki
;
Hayashihara, Yuya
;
Yokota, Shione
;
Chivapreecha, Sorawat
;
Moungnoul, Phichet
FPGAs (Field-Programmable Gate Arrays) with reconfigurable features are used in various applications. However, circuits on FPGAs are inferior to circuits on ASICs in operating frequency, power consumption, and area. Co-design of FPGA and ASIC is one way to solve this problem. To realize this co-design, RTL-Designed FPGAs have been proposed by the authors. The features of the FPGAs are that they can be described only with HDL and that they can be realized with ordinary standard cells. Therefore, FPGAs and ASICs can be co-designed easily. Until now, the FPGAs have not been considered for optimal wiring count. In this paper, we clarify the optimum number of wires using a 4-bit adder circuit. In addition, cases in which more than that optimal number of wires is needed are discussed.
Some of the metrics are blocked by your
consent settings
Design and Implementation of Multiphase Digital Oscillator
(2024-01-01)
Jongsataporn, Thitaphan
;
Yospanya, Poonna
;
Chivapreecha, Sorawat
This paper presents a design and implementation of the multiphase digital oscillator, which can determine the initial phase of multi-output signals to desired initial phases. The proposed system consists of biquad digital oscillator to oscillate the reference signal, and the new phase shifters which are first order IIR filters that can shift the phase of signals at a specified frequency to give them the desired phases. Design example and simulation results will be shown. Moreover, real-time hardware implementation on STM32 digital signal processor can be demonstrated to confirm the proposed design can work with hardware experimental results.
Some of the metrics are blocked by your
consent settings
Real-Time Zero-Phase Digital Filter Using Recurrent Neural Network
(2023-01-01)
Sinjanakhom, Tantep
;
Chivapreecha, Sorawat
This paper proposes a method to design and implement a zero-phase digital filter that can run in a real-time system. Generally, zero-phase filters are designed for non-causal systems only as the time-reversal operations are required. Thus, the typical usage of these filters is for offline applications. For this reason, we propose a real-time zero-phase digital filter that is designed based on a recurrent neural network model, particularly the gated recurrent units. The model learns to perform zero-phase filtering by using training data made from the filtered signals that are generated by using the conventionally designed zero-phase filter. The original digital filter used to create the dataset is an IIR filter performing forward-backward filtering. The best trained model yields the mean absolute loss values at approximately 0.001 and can process at least 30 times faster than real-time. Furthermore, the trained model was implemented as a 3-band zero-phase graphic equalizer to exhibit one of its applications.

KMITL

Browse

Filters

Settings

Sort By

Results per page

Search Results