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Efficient Design of Read Voltages and LDPC Codes in NAND Flash Memory Using Density Evolution
(2023-01-01)
Duangthong, Chatuporn
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Phakphisut, Watid
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Wardkein, Paramote
Low-density parity-check (LDPC) codes play an important role in the reliability enhancement of commercial NAND flash memory. Unfortunately, due to the requirement of the reading speed of NAND flash memory, the LDPC decoder will not obtain precise soft information to achieve high error-correcting capability. In this work, we use a density evolution (DE) algorithm to reveal the decoding threshold of the LDPC decoder affected by the read voltages. We propose the efficient design of read voltages so that the LDPC decoder has the lowest decoding threshold. Therefore, this method can guarantee that the designed read voltages are suitable for a given LDPC code. Moreover, since we found that the designed read voltages are related to the structure of the LDPC code, the joint design of the read voltages and LDPC code is then proposed to achieve the capacity of NAND flash memory. The simulation results demonstrate that our proposed design significantly improves the frame error rate (FER) performance of NAND flash memory.
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Development of High Efficient LDPC Encoder for Deep Space Applications
(2023-01-01)
Srisupha, Thanat
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Wongsa, Anusorn
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Duangthong, Chatuporn
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Phakphisut, Watid
In this paper, we present the design and implementation of a high efficient low-density parity-check (LDPC) encoder for deep space applications. The proposed encoder utilizes the generator matrix of CCSDS LDPC codes to simplify the encoding process and reduces the complexity of hardware implementation. The proposed encoder has two types. The first type aims to design a low-complexity architecture and flexibility. The second type presents high throughput architecture, allowing the user to choose the appropriate type according to their usage condition. The results of FPGA synthesis show that the proposed LDPC encoders achieve flexibility, low complexity, and high throughput.
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5G Channel Coding Tool: Learning and Performance Evaluation
(2023-01-01)
Mueadkhunthod, Krittiyaporn
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Wongsa, Anusorn
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Srisupha, Thanat
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Duangthong, Chatuporn
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Puntsri, Kidsanapong
The 5G channel coding tool is presented to explain channel coding in 5G New Radio (NR). Our tool consists of six modules such as information generator, channel encoder, modulator, noise generator, demodulator, and channel decoder. The channel encoder and modulator are developed according to 3GPP TS 38.212 and 3GPP TS 38.211 technical specifications, respectively. The 5G channel coding tool provides a graphical user interface (GUI) in which users can study the block diagrams of downlink and uplink process. In addition, our 5G channel coding tool can be used to evaluate the bit error rate performance of 5G channel coding in additive white Gaussian noise (AWGN) and fading channels.
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Two-Dimensional Error Correction Code for Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) Caches
(2022-09-01)
Duangthong, Chatuporn
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Supnithi, Pornchai
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Phakphisut, Watid
Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) is an emerging nonvolatile memory (NVM) technology that can replace conventional cache memory in computer systems. STT-RAM has many desirable properties such as high writing and reading speed, non-volatility, and low power consumption. Since the cache requires a high speed of writing and reading speed, a single-error correction and double error detection (SEC-DED) are applicable to improve the reliability of the cache. However, the process variation and thermal fluctuation of STT-MRAM cause errors. For example, writing ‘1’ bits has more errors than writing ‘0’ bits. We then design the weight reduction code to reduce the error caused by writing ‘1’ bits. Moreover, the performance of an SEC-DED code is improved by constructing an SED-DED code as the product code. The simulation results demonstrate that the two-dimensional error correction code consisting of product code and weight reduction code is roughly 5:67×10<sup>-4</sup> lower than the SEC-DED code when the error rate of writing ‘1’ bits is equal to 6 ×10<sup>-3</sup>.
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Design of Lookup-Table (LUT) Decoder for Protograph-Based Low-Density Parity-Check (LDPC) codes
(2022-01-01)
Duangthong, Chatuporn
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Phakphisut, Watid
The Belief-propagation (BP) algorithm is a powerful decoder for LDPC codes. However, the BP algorithm requires the high complexity of the check node operation. Therefore, in the previous works, a lookup table (LUT)-based decoder has been proposed for LDPC codes. In this work, we propose the LUT design for protograph LDPC codes. Our LUT design can support the parallel edge, variable node with degree-1 and punctured variable node. As a result, the coding losses of 2-, 3-and 4-bit quantization of LUT decoder are 1.6, 0.5 and 0.1 dB compared to BP algorithm.
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Development of 5G Polar Experimental Kit
(2022-01-01)
Wongsa, Anusorn
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Mueadkhunthod, Krittiyaporn
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Phakphisut, Watid
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Duangthong, Chatuporn
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Puntsri, Kidsanapong
The 5G polar experimental kit is presented for learning polar codes in 5G new radio. The experimental kit is developed to demonstrate the eleven encoding processes of polar codes described in 3GPP TS 38.212 technical specification. The experimental kit provides a graphical user interface (GUI) which a user can provide any the input parameters defined in the 5G new radio. The experimental kit provides a software and a hardware for a 5G polar encoder. After the polar encoder in the software or the hardware are done, the encoding results will be displayed on the GUI along with their processes details.
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Joint design of channel output quantizer and LUT-Based LDPC decoder
(2021-05-19)
Duangthong, Chatuporn
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Supnithi, Pornchai
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Phakphisut, Watid
Recently, the LUT-based LDPC decoder has been designed by maximizing mutual information, where the performances of channel output quantizer and LUT-based decoder are considered separately. In this work, we propose the joint design of the channel output quantizer and LUT-based decoder. Our joint design aims to minimize the error probability of LDPC decoding through the density evolution algorithm. We found that the joint design outperforms the previous work at the waterfall region.
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Capacity Enhancement of Asymmetric Multi-Level Cell (MLC) NAND Flash Memory using Write Voltage Optimization
(2019-06-01)
Duangthong, Chatuporn
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Phakphisut, Watid
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Supnithi, Pornchai
In NAND flash memory, the number of bits per cell is increased to enhance the storage density, however, the reliability of NAND flash memory will be degraded. The current research only focuses on the read voltage optimization and advanced error-correction codes. The investigation of the write voltages optimization is limited. Since the write voltages significantly affect the channel capacity, we propose the write voltage optimization to enhance the channel capacity of MLC NAND flash memory. The differential evolution algorithm is applied to find the optimal write voltage that provide the maximum channel capacity.
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Read Voltage Optimization in MLC NAND Flash Memory via the Density Evolution
(2019-04-01)
Duangthong, Chatuporn
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Phakphisut, Watid
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Supnithi, Pornchai
The multi-level-cell (MLC) NAND flash memory can typically use multiple reads for obtaining soft information for the LDPC decoder. The multiple reads give the soft information which is quantized to a certain level. The major challenge is that the read voltages must be precisely selected to provide better soft information. In the previous work, the read voltages are selected so that the soft information has the maximum mutual information (MMI). However, the error-correction capability of LDPC decoder is not considered. Therefore, in this work, we analyze the performance of LDPC decoder by density evolution whereby the soft information is quantized. Then the optimal read voltages for given LDPC codes are obtained. As a result, for a regular LDPC code with the read voltages optimized by density evolution can provide the lower BER performance compared with the MMI technique.
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Search algorithm of write voltage optimization in NAND flash memory
(2017-10-19)
Duangthong, Chatuporn
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Phakphisut, Watid
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Supnithi, Pornchai
In NAND flash memory, the major problem is voltage immigration which is the result of program and erase (PE) cycling number and data retention time. Although previous works study the write voltage optimization for NAND flash memory, the write voltage optimization of multilevel coding (MLC) and bitinterleaved coded modulation (BICM) structure have not been focused, therefore, in this work, we propose the search algorithm of write voltage optimization for MLC and BICM structure. The search algorithm can reduce the number of possible write voltages and provides the optimal write voltage for each PE cycling number. The bit-error rate (BER) performance of optimized write voltage is lower than the fixed write voltage in BICM structure. Moreover, the proposed optimization technique provides the most significant bit (MSB) and least significant bit (LSB) of MLC structure with identical BER performances.

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