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Author: search.filters.author.Higuchi, KohjiSubject: search.filters.subject.wave-pipeline

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    Designing a Fine-Tuning Tool for Machine Learning with High-Speed and Low-Power Processing
    (2018-12-24)
    Sato, Tomoaki
    ;
    Chivapreecha, Sorawat
    ;
    Higuchi, Kohji
    ;
    Moungnoul, Phichet
    Machine learning is used in various fields. In order to broaden its further applications, it is necessary to use an architecture that operates faster and with lower-power consumption than conventional architecture. In this paper, as an architecture for that, it is proposed to use the ASIC-FPGA architecture proposed by the authors. In circuits on FPGAS, wave-pipeline techniques can be introduced for further high through put processing. In order to further improve the performance of wave-pipelines on the FPGAS, fine-Tuning should be executed. A fine-Tuning tool essential for realizing these is developed.
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    RCA on FPGAs designed by the RTL design methodology and wave-pipelined operation
    (2016-09-06)
    Sato, Tomoaki
    ;
    Chivapreecha, Sorawat
    ;
    Moungnoul, Phichet
    ;
    Higuchi, Kohji
    Field-programmable gate arrays (FPGAs) are used in various systems that use reconfigurable function. Conventional FPGAs have been developed by a transistor-level description for minimizing routing delay. Although FPGAs developed by the register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the authors have advanced their development. They should be shown to operate in a practical throughput. For this purpose, circuits on them need to be designed and evaluated. In this paper, a ripple-carry adder (RCA) is designed on them and the throughput of the RCA is evaluated. The throughput shows that it is applicable to network processors. In addition, a wave-pipelined operation without changing the RCA reveals that the problem of routing delay in the FPGAs developed by the RTL methodology is mitigated.
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    Evaluations of waved-shift registers for the multiplexed bus
    (2014-10-15)
    Sato, Tomoaki
    ;
    Moungnoul, Phichet
    ;
    Chivapreecha, Sorawat
    ;
    Higuchi, Kohji
    In this Paper, waved-shift registers for the multiplexed bus are developed and evaluated. The multiplexed bus is needed for HIPS (Host-based Intrusion Prevention System) in 4G mobile communications. Because an FPGA (Field-Programmable Gate Array) has been used for the multiplexed bus, there is a problem where it doesn't work at over 1 GHz. Then, the use of the FPGA leads to increase in power consumption. In this work, by using 180 nm C-MOS (Complementary Metal-Oxide Semiconductor) technology, waved-shift registers necessary for the multiplexed bus are developed. Furthermore, the comparative evaluations of the waved-shift registers are executed by using the conventional shift register that operates at 2GHz. As a result, the waved-shift registers are revealed to have surpassed all the points of throughput, power consumption and area.