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Author: search.filters.author.Higuchi, Kohji

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    Designing a Fine-Tuning Tool for Machine Learning with High-Speed and Low-Power Processing
    (2018-12-24)
    Sato, Tomoaki
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    Chivapreecha, Sorawat
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    Higuchi, Kohji
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    Moungnoul, Phichet
    Machine learning is used in various fields. In order to broaden its further applications, it is necessary to use an architecture that operates faster and with lower-power consumption than conventional architecture. In this paper, as an architecture for that, it is proposed to use the ASIC-FPGA architecture proposed by the authors. In circuits on FPGAS, wave-pipeline techniques can be introduced for further high through put processing. In order to further improve the performance of wave-pipelines on the FPGAS, fine-Tuning should be executed. A fine-Tuning tool essential for realizing these is developed.
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    A detection method of web authentication problems for mobile devices corresponding to IEEE 802.11ac
    (2018-05-30)
    Sato, Tomoaki
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    Chivapreecha, Sorawat
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    Higuchi, Kohji
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    Moungnoul, Phichet
    Improvement in the performance of mobile devices makes many opportunities to watch high resolution moving images using a public Wi-Fi LAN service. A web authentication may be required to specify the network user when accessing the public Wi-Fi LAN service. For some authentications, Google, Facebook and Twitter accounts are used. Although the use of these accounts provides convenience, it has serious problems. If the website for the authentication is a phishing site, the account may be abused. The reason is that it is difficult for many users to identify phishing sites. The identification using the CPU of a mobile device has a problem that it cannot deal with the throughput of IEEE 802.11ac. In this article, problems with web authentications used in public Wi-Fi LAN services are surveyed. Then, the authors propose a detection method of the problems that can deal with the throughput realized by IEEE 802.11ac and can process with low-power operations on mobile devices.
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    Throughput of a Firewall Unit on FPGAS Developed by the RTL Design Methodology
    (2017-10-19)
    Sato, Tomoaki
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    Chivapreecha, Sorawat
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    Moungnoul, Phichet
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    Higuchi, Kohji
    The transmission speed of mobile communication systems for mobile and IoT (Internet of things) devices is getting faster. Advanced, high-speed and low-power processing on network packets are needed in these devices. To realize these performances in the devices, the authors have proposed FPGAS (field-programmable gate arrays) which are developed by the RTL (register-Transfer level) design methodology. As an application of the FPGAS for mobile communication systems, a firewall unit has been developed. However, the function of the firewall unit is only packet filtering. A function for deleting a packet passing through an unauthorized port has not been realized. In this paper, the authors design the firewall unit with the function of deleting the packet. The throughputs of the firewall unit are shown. Thus, it is clarified that high throughput can be accommodated.
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    RCA on FPGAs designed by the RTL design methodology and wave-pipelined operation
    (2016-09-06)
    Sato, Tomoaki
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    Chivapreecha, Sorawat
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    Moungnoul, Phichet
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    Higuchi, Kohji
    Field-programmable gate arrays (FPGAs) are used in various systems that use reconfigurable function. Conventional FPGAs have been developed by a transistor-level description for minimizing routing delay. Although FPGAs developed by the register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the authors have advanced their development. They should be shown to operate in a practical throughput. For this purpose, circuits on them need to be designed and evaluated. In this paper, a ripple-carry adder (RCA) is designed on them and the throughput of the RCA is evaluated. The throughput shows that it is applicable to network processors. In addition, a wave-pipelined operation without changing the RCA reveals that the problem of routing delay in the FPGAs developed by the RTL methodology is mitigated.
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    An FPGA architecture for ASIC-FPGA co-design to streamline processing of IDSs
    (2016-01-01)
    Sato, Tomoaki
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    Chivapreecha, Sorawat
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    Moungnoul, Phichet
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    Higuchi, Kohji
    Novel methods for unauthorized access are always made. For cyber security measures in mobile devices, low-power and high-speed processing is very important. Despite these situations, a CPU for mobile devices is a very low processing capacity in order to focus on low-power operations and does not have sufficient performance for processing detection processing for unauthorized access. In contrast, a field-programmable gate array (FPGA) can apply to cyber security processing on mobile devices. By using the FPGA, cyber security processing is able to use parallel processing, super pipeline and processing that is independent of a word width size. However, the FPGA has a problem that the delay times of arithmetic circuits are longer than that of an application specific integrated circuit (ASIC) or CPU. In this paper, the authors propose an FPGA architecture for ASIC-FPGA co-design for addressing the problem. In order to evaluate the architecture, adders are enhanced by ASIC-FPGA co-design and evaluated. As a result, it is shown that the problem with the delay times of arithmetic circuits is solved.
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    Evaluations of waved-shift registers for the multiplexed bus
    (2014-10-15)
    Sato, Tomoaki
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    Moungnoul, Phichet
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    Chivapreecha, Sorawat
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    Higuchi, Kohji
    In this Paper, waved-shift registers for the multiplexed bus are developed and evaluated. The multiplexed bus is needed for HIPS (Host-based Intrusion Prevention System) in 4G mobile communications. Because an FPGA (Field-Programmable Gate Array) has been used for the multiplexed bus, there is a problem where it doesn't work at over 1 GHz. Then, the use of the FPGA leads to increase in power consumption. In this work, by using 180 nm C-MOS (Complementary Metal-Oxide Semiconductor) technology, waved-shift registers necessary for the multiplexed bus are developed. Furthermore, the comparative evaluations of the waved-shift registers are executed by using the conventional shift register that operates at 2GHz. As a result, the waved-shift registers are revealed to have surpassed all the points of throughput, power consumption and area.
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    Performance estimates of an embedded CPU for high-speed packet processing
    (2014-01-01)
    Sato, Tomoaki
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    Moungnoul, Phichet
    ;
    Chivapreecha, Sorawat
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    Higuchi, Kohji
    This paper states an embedded CPU performance required for processing packets at a continuous throughput of 1 Gbps. And the out-of-order execution of packets is proposed for processing a variety of packet frame size in the CPU performance. Despite the requirement of high-speed network connections in embedded devices and mobile devices, it is not realized that an embedded CPU capable of high-speed packet processing with low-power operations. In this paper, the authors estimate operating frequencies for processing packets at a continuous throughput of 1 Gbps using a MIPS architecture which is widely used for network devices or embedded systems today. Then, the cases that must be processed with a high-spec CPU is revealed, the solution is proposed. When the frequency of 1.0 GHz and 64-bit registers are used, the CPU usage is 11.0 %. © 2014 IEEE.
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    System design of durian maturity determination using microstrip patch antennas
    (2007-12-01)
    Kittiamornkul, Navapadol
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    Jiraseriamornkul, Kamon
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    Chamnongthai, Kosin
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    Krairiksh, Monai
    ;
    Higuchi, Kohji
    Since Durian has specific properties such as big peel, non-uniform shape, rough skin, etc, the system design of non-destructive maturity determination is hard to perform. This paper proposes the system designing of durian maturity determination using microstrip patch antennas operating 2.45 GHz of microwave frequency and the measurement system which can adjust size, height, etc., to make closed environment. This method can protect the reflection of microwave to environment and measure durian in every size. The results show that this technique can provide fast durian maturity determination at accuracy of 72.22%. © 2007 SICE.