KMITL

Permanent URI for this communityhttps://dspace.kmitl.ac.th/handle/123456789/1

Browse

Settings

Author: search.filters.author.Moungnoul, PhichetSubject: search.filters.subject.ASIC

Search Results

Now showing 1 - 3 of 3
  • Loading...
    Thumbnail Image
    Some of the metrics are blocked by your 
    consent settings
    Item type:Item,
    Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration
    (2025-01-01)
    Sato, Tomoaki
    ;
    Murakami, Anyu
    ;
    Chivapreecha, Sorawat
    ;
    Moungnoul, Phichet
    This paper explores the evaluation and optimization of multi-bit input logic blocks (LBs) within RTL-designed FPGA architectures. Traditional FPGA designs face limitations in power consumption, delay, and area due to the constraints of reconfigurable circuits. The proposed architecture leverages RTL-level design capabilities to address these challenges and enables the co-design of FPGAs and ASICs. The authors evaluate the performance of 8-bit, 16-bit, and 32-bit input LBs in terms of delay, area, and synthesis feasibility. The results demonstrate that 8-bit input LBs achieve a delay of 0.68 ns with an area of 2202.48 μm<sup>2</sup>, outperforming multi-stage smaller LBs. Although 16-bit input LBs show potential for delay reduction, their synthesis demands significant time and results in a large area footprint, rendering them impractical. Synthesis of 32-bit input LBs was not feasible due to current tool limitations. These findings highlight the effectiveness of 8-bit input LBs for pattern matching tasks and emphasize the importance of application-specific optimization. The fixed routing feature of RTL-designed FPGAs facilitates the development of efficient, customizable designs tailored to specific workloads. This work contributes to the advancement of FPGA architectures, offering insights for future research on larger input LBs and their integration into high-performance applications.
  • Loading...
    Thumbnail Image
    Some of the metrics are blocked by your 
    consent settings
    Item type:Item,
    Optimal Number of Wires for Circuits on RTLDesigned FPGAs
    (2024-01-01)
    Sato, Tomoaki
    ;
    Hayashihara, Yuya
    ;
    Yokota, Shione
    ;
    Chivapreecha, Sorawat
    ;
    Moungnoul, Phichet
    FPGAs (Field-Programmable Gate Arrays) with reconfigurable features are used in various applications. However, circuits on FPGAs are inferior to circuits on ASICs in operating frequency, power consumption, and area. Co-design of FPGA and ASIC is one way to solve this problem. To realize this co-design, RTL-Designed FPGAs have been proposed by the authors. The features of the FPGAs are that they can be described only with HDL and that they can be realized with ordinary standard cells. Therefore, FPGAs and ASICs can be co-designed easily. Until now, the FPGAs have not been considered for optimal wiring count. In this paper, we clarify the optimum number of wires using a 4-bit adder circuit. In addition, cases in which more than that optimal number of wires is needed are discussed.
  • Loading...
    Thumbnail Image
    Some of the metrics are blocked by your 
    consent settings
    Item type:Item,
    An FPGA architecture for ASIC-FPGA co-design to streamline processing of IDSs
    (2016-01-01)
    Sato, Tomoaki
    ;
    Chivapreecha, Sorawat
    ;
    Moungnoul, Phichet
    ;
    Higuchi, Kohji
    Novel methods for unauthorized access are always made. For cyber security measures in mobile devices, low-power and high-speed processing is very important. Despite these situations, a CPU for mobile devices is a very low processing capacity in order to focus on low-power operations and does not have sufficient performance for processing detection processing for unauthorized access. In contrast, a field-programmable gate array (FPGA) can apply to cyber security processing on mobile devices. By using the FPGA, cyber security processing is able to use parallel processing, super pipeline and processing that is independent of a word width size. However, the FPGA has a problem that the delay times of arithmetic circuits are longer than that of an application specific integrated circuit (ASIC) or CPU. In this paper, the authors propose an FPGA architecture for ASIC-FPGA co-design for addressing the problem. In order to evaluate the architecture, adders are enhanced by ASIC-FPGA co-design and evaluated. As a result, it is shown that the problem with the delay times of arithmetic circuits is solved.