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Author: search.filters.author.Moungnoul, PhichetSubject: search.filters.subject.Mobile devices

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    Throughput of a Firewall Unit on FPGAS Developed by the RTL Design Methodology
    (2017-10-19)
    Sato, Tomoaki
    ;
    Chivapreecha, Sorawat
    ;
    Moungnoul, Phichet
    ;
    Higuchi, Kohji
    The transmission speed of mobile communication systems for mobile and IoT (Internet of things) devices is getting faster. Advanced, high-speed and low-power processing on network packets are needed in these devices. To realize these performances in the devices, the authors have proposed FPGAS (field-programmable gate arrays) which are developed by the RTL (register-Transfer level) design methodology. As an application of the FPGAS for mobile communication systems, a firewall unit has been developed. However, the function of the firewall unit is only packet filtering. A function for deleting a packet passing through an unauthorized port has not been realized. In this paper, the authors design the firewall unit with the function of deleting the packet. The throughputs of the firewall unit are shown. Thus, it is clarified that high throughput can be accommodated.
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    An FPGA architecture for ASIC-FPGA co-design to streamline processing of IDSs
    (2016-01-01)
    Sato, Tomoaki
    ;
    Chivapreecha, Sorawat
    ;
    Moungnoul, Phichet
    ;
    Higuchi, Kohji
    Novel methods for unauthorized access are always made. For cyber security measures in mobile devices, low-power and high-speed processing is very important. Despite these situations, a CPU for mobile devices is a very low processing capacity in order to focus on low-power operations and does not have sufficient performance for processing detection processing for unauthorized access. In contrast, a field-programmable gate array (FPGA) can apply to cyber security processing on mobile devices. By using the FPGA, cyber security processing is able to use parallel processing, super pipeline and processing that is independent of a word width size. However, the FPGA has a problem that the delay times of arithmetic circuits are longer than that of an application specific integrated circuit (ASIC) or CPU. In this paper, the authors propose an FPGA architecture for ASIC-FPGA co-design for addressing the problem. In order to evaluate the architecture, adders are enhanced by ASIC-FPGA co-design and evaluated. As a result, it is shown that the problem with the delay times of arithmetic circuits is solved.
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    Packet filtering circuits for smart phones
    (2012-12-01)
    Sato, Tomoaki
    ;
    Moungnoul, Phichet
    ;
    Fukase, Masa Aki
    Security measures for smart phones are important. Anti-virus software for smart phones can be used and the process consumes CPU resources. The CPUs of them are powerless CPU for an embedded system and those operations consume battery power. In this paper, the authors propose packet filtering circuits for smart phones. The packet filtering circuits are a firewall. Using the firewall is a means to protect smart phones from computer viruses and unauthorized access. In addition, they are used to control the power consumption and to reduce of detecting units for unauthorized access. The features of the circuits are to achieve those functions without reconstructing circuits. The operations of the circuits are verified by gate-level simulations.
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    Delay time analysis of reconfigurable firewall unit
    (2011-12-01)
    Sato, Tomoaki
    ;
    Moungnoul, Phichet
    ;
    Fukase, Masa Aki
    A firewall function is indispensable for mobile devices and it demands low-power operations. To realize this demand, the authors have developed a firewall unit with a reconfigurable device. The firewall unit needs a large amount of register for the timing adjustment of packets. Using the registers is the cause of power consumption. In this paper, to solve the problem of power consumption, the firewall unit has developed by using wave-pipelining technique and detailed delay time for the technique is analyzed.