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Two CMOS Wilkinson Power Dividers Using High Slow-Wave and Low-Loss Transmission Lines
(2024-08-01)
Pakasiri, Chatrpol
;
Teng, Wei Sen
;
Wang, Sen
This work presents two Wilkinson power dividers (WPDs) using multi-layer pseudo coplanar waveguide (PCPW) structures. The PCPW-based WPDs were designed, implemented, and verified in a standard 180 nm CMOS process. The proposed PCPW features high slow-wave and low-loss performances compared to other common transmission lines. The two WPDs are based on the same PCPW structure parameters in terms of line width, spacing, and used metal layers. One WPD was realized in a straight PCPW-based layout, and the other WPD was realized in a meandered PCPW-based layout. Both the two WPDs worked up to V-band frequencies, as expected, which also demonstrates that the PCPW guiding structure is less susceptible to the effects of meanderings on the propagation constant and characteristic impedance. The meandered design shows that the measured insertion losses were about 5.1 dB, and its return losses were better than 17.5 dB at 60 GHz. In addition, its isolation, amplitude imbalance, and phase imbalance were 18.5 dB, 0.03 dB, and 0.4°, respectively. The core area was merely 0.2 mm × 0.23 mm, or 1.8 × 10−3λ<inf>o</inf>2.
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A Compact 0.73~3.1 GHz CMOS VCO Based on Active-Inductor and Active-Resistor Topology
(2024-06-01)
Pakasiri, Chatrpol
;
Hsu, Ke Chung
;
Wang, Sen
In this paper, a wideband VCO that covers popular Long-Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz frequencies is designed and developed in a standard 0.18 μm CMOS process. The VCO utilizes active inductors to achieve coarse-tuning of the inductance and a compact chip area. Moreover, an active feedback resistor is introduced into the active inductor for fine-tuning of the inductance. The feedback resistor also affects the equivalent resistance of the active inductor; therefore, wide inductance tuning and low power consumption can be obtained by optimizing the resistor. The core area of the fabricated CMOS chip is merely 0.046 mm2, excluding all testing pads. With a 6.7~10.1 mW DC consumption, the measured oscillation frequencies range from 0.73 GHz to 3.1 GHz, which demonstrates a 123.8% tuning range. At the frequencies of interest, the measured phase noises are from −80.7 to −84.5 dBc/Hz at a 1 MHz offset frequency.
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A 10 GHz Compact Balun with Common Inductor on CMOS Process
(2023-01-01)
Pakasiri, Chatrpol
;
Xu, Jian Long
;
Wang, Sen
This paper presents a compact balun with a common inductor design. The design used Wilkinson-type balun topology with modified lumped transmission lines and a common inductor to realize circuit size reduction on a lossy CMOS process. Measurements of the prototype chip had a reflection coefficient below 17.8 dB at all ports, an insertion loss of 1.98 dB, and an isolation of 16.8 dB. The chip size was only 0.025λ<inf>0</inf> × 0.034λ<inf>0</inf>.
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A low-phase-noise and low-power CMOS colpitts VCO using Gm boosting and capacitance switching techniques
(2021-01-01)
Pakasiri, Chatrpol
;
You, Jia Hao
;
Wang, Sen
This letter presents a low-power and low-phase-noise 5-GHz VCO fabricated in a standard CMOS 0.18-μm process. The low power dissipation was achieved by using the PMOS cross-coupled pair and G<inf>m</inf>-boosting topology, and the low phase noise was obtained by adding two pairs of switched capacitor array. The VCO consumed a dc power of 2.92 mW with the supply voltage of 1 V. The measured phase noises were − 104.6 dBc/Hz and − 117.4 dBc/Hz at 1 MHz offset frequency with switched off and on capacitances, respectively, which demonstrated 12.8-dB improvement.
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Compact Wilkinson Power Divider Using Composite Right/Left-Handed Transmission Line on CMOS Process
(2020-03-01)
Nithiporndecha, Kittipong
;
Wang, Sen
;
Pakasiri, Chatrpol
This paper shows the design and analysis of CMOS Wilkinson power divider using composite right/left-handed transmission lines. The effects of lossy components in the circuit are also analyzed. The circuit is then implemented on a 0.18-μm CMOS process. The return losses are less than -16 dB, the isolation is better than -26 dB, and the insertion losses are better than -5.15 dB at the frequencies of interest. Its chip size is 0.5 mm2 (9.9e-5λ<inf>o</inf>2) including testing pads.
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A 4-bit ultra-wideband complementary metal-oxide-semiconductor attenuator with low root-mean-square amplitude error
(2019-11-01)
Pakasiri, Chatrpol
;
Zhu, Fu Sheng
;
Wang, Sen
This article presents the 4-bit ultra-wideband complementary metal-oxide-semiconductor (CMOS) attenuator in a standard 0.18-μm CMOS process. This design adopts switched bridge-T type topologies for each attenuation bit. Based on insertion losses and input P<inf>1-dB</inf> considerations, the circuit performances can be optimized by the proper bit ordering arrangement. Therefore, the bit ordering 0.5-4-2-1 dB is employed in the 4-bit attenuator. Moreover, series inductors are added between each bit to further improve the input and output return losses. Measured results demonstrate that the attenuation range of the circuit is 7.5 dB with 0.5 dB step and the root-mean-square (RMS) amplitude error is between 0.11 and 0.13 dB from 3.1 to 10.8 GHz. The differences between simulated and measured RMS amplitude errors are less than 0.2 dB, which demonstrates the good agreement and feasibility of the design concept. The measured input P<inf>1-dB</inf> is 15 dBm at 5 GHz and the chip area is 1.12 mm2 including all testing pads.

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