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A compact floating and grounded memristor model using single active element
(2022-12-01)
Prasad, Sagar Surendra
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Kumar, Prashant
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Raj, Niranjan
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Sharma, Pankaj Kumar
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Priyadarshini, Bindu
Memristor with defined operational specifications is a challenging task that promotes innovation in emulation circuit modelling. This article presents a single active block based compact memristor emulator architecture which is suitable for both floating and grounded circuit topologies. It effectively operates in incremental/decremental modes in both the configurations. The proposed model utilizes only one Differential Voltage Current Conveyor Transconductance Amplifier (DVCCTA) as an active block along with a few passive components. It discourages the use of extra sub-circuit components like multiple active blocks, summers and multipliers. The circuit is intended to work at ±1 V of dc power supply and has a power consumption of 8.74 mW. The proposed emulator model exhibits all the characteristics of an ideal memristor with an operating frequency of 12.8 MHz. It has wide working voltage range of 50–500 mV. The memristor model is built and simulated using the TSMC 0.18 μm CMOS process parameter. The reliability and effectiveness of the proposed model is verified through non-ideal, Monte-Carlo, process corner, non-volatility and temperature variation analysis. Furthermore, the memristor prototype is constructed on the breadboard using discrete ICs AD844AN and CA3080. The experimental outcome is found in accordance with the simulation. The applicability of the proposed memristor model is verified by implementing a memristor based Schmitt trigger circuit.
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Current-Mode Square-Rooting Circuit Based on CMOS Translinear
(2018-08-20)
Wongprommoon, Natapong
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Thongdit, Preecha
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Prommee, Pipat
In this paper, a new current-mode square-rooting circuit based on translinear principle is proposed. The saturation mode of MOS transistors is used for realizing the proposed circuit with ± 1.5V power supplies. Square-rooting circuit is realized from the translinear type-A and current computation which uses totally eighteen MOS transistors. The circuit has two inputs which one performs as input and another one for a variable gain. Two input positions are similar characteristic which are able to swap generally. The gain of proposed square-rooting can be electronically tuned by bias current. The current output is accurately compared with the ideal square-rooting function. The error at current output is achieved lower than 4%along 150μA of input range. High frequency sinusoidal signal can be operated up to 5MHz. The proposed circuit is suitable for applying in the varieties of analogue signal-processing applications. The simulation results are depicted to confirm the theoretical analysis by using PSpice. Moreover, layout and post layout simulation results are included.
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Integrable CMOS-Based Current-Mode Sinusoidal Frequency and Peak Detector
(2017-12-01)
Prommee, Pipat
This research proposes the integrable CMOS current-mode instantaneous frequency and peak detector (FPD) based on the trigonometric relationships and mathematic algorithm without the divider function and low-pass filter. The proposed FPD structure is straightforward, consisting of two differentiators, two multipliers and one square-rooter. The input of FPD is operable in the 20–100 kHz frequency and 20–100 μ A amplitude under ± 1.5 V power supplies. In the research, the FPD was simulated using the current-mode CMOS technology and a prototype detector subsequently materialized using the commercially available components. In addition, the FPD was experimentally utilized as the FM and AM demodulators with very satisfactory demodulation outcomes. The simulation and experimental results were agreeable and also consistent with the trigonometric relationships and algorithmic scheme. More importantly, the integrable FPD could achieve the high-accuracy current output and fast response.
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Electronically tunable MOS-only current-mode high-order band-pass filters
(2017-01-01)
Prommee, Pipat
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Tiamsuphat, Aphinat
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Taher Abuelma'Atti, Muhammad
This paper presents new CMOS current-mode ladder Chebyshev and elliptic band-pass filters (BPFs). The signal flow graph and the network transformation methods are used to synthesize the proposed BPFs by using Chebyshev and elliptic RLC low-pass prototypes. CMOS-based lossy and lossless integrators with grounded capacitors are used to synthesize the proposed BPFs. The proposed filters can be electronically tuned between 10 kHz and 100 MHz by adjusting the bias current from 0.02 A to 200 A. Both filters use a 1.5 V DC power supply, which leads to low dynamic power consumption. Both filters enjoy total harmonic distortion of less than 1.5% along the range of the tuning bias currents. Simulation results are included to illustrate the functionality of the proposed filters.
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CMOS-based current-mode tunable ladder Elliptic low-pass filter
(2015-10-09)
Prommee, Pipat
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Kunto, Terdsak
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Somdunyakanok, Montri
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Prommee, Tanakrit
This paper presents a tunable CMOS-based third-order low-pass filter that can be operated in high frequency. The proposed low pass filter is designed based on Elliptic Ladder low-pass filter prototype. The proposed filter structure is constructed by using two lossy integrators and a lossless integrator. The proposed filter comprises only 18 transistors. The frequency responses of low-pass filter can be electronically tuned between 10kHz and 100MHz through bias current from 0.01 μA to 100 μA. The circuit used 1.5 V power supply with 3mW power consumption at 100 μA bias current. Using of the grounded capacitors which is suitable for further integration. THD of low-pass filter can be obtained less than 1% along the operating frequencies. PSPICE simulation results are carried out to confirm the theory by using TSMC 0.18μm technology.
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CMOS-based Chebyshev current-mode ladder band-pass filter
(2015-04-24)
Tiamsuphat, Aphinat
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Prommee, Pipat
This paper presents a CMOS-based Chebyshev current-mode ladder band-pass filter (BPF). The integrator building blocks (lossy and lossless integrators) with 6 grounded capacitors are used to realize the BPF by using doubly terminated RLC ladder filter prototype based on TSMC 0.18μm CMOS technology. Frequency response of the circuit can be tuned between 1MHz and 200MHz through bias currents from 0.01 μA to 100 μA. The proposed circuit has many attractive features, for instant, low power supply as 1.5V, low dynamic power consumption and low Total Harmonic Distortion (THD). All simulation results are carried out by PSpice which are good agreements compared with the RLC prototype.
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Electronically tunable current-mode high-order ladder low-pass filters based on CMOS technology
(2015-01-01)
Kunto, Terdsak
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Prommee, Pipat
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Abuelma'atti, Muhammad Taher
This paper describes the design of current mode low-pass ladder filters based on CMOS technology. The filters are derived from passive RLC ladder filter prototypes using new CMOS lossy and lossless integrators. The all-pole and Elliptic approximations are used in the proposed low-pass filter realizations. The proposed two types of filter can be electronically tuned between 10 kHz and 100 MHz through bias current from 0.03 μA to 300 μA. The proposed filters use 1.5 V power supply with 3 mW power consumption at 300 μA bias current. The proposed filters are resistorless, use grounded capacitors and are suitable for further integration. The total harmonic distortion (THD) of the low-pass filters is less than 1% over the operating frequency range. PSPICE simulation results, obtained by using TSMC 0.18μm technology, confirm the presented theory.

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