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Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration
(2025-01-01)
Sato, Tomoaki
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Murakami, Anyu
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Chivapreecha, Sorawat
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Moungnoul, Phichet
This paper explores the evaluation and optimization of multi-bit input logic blocks (LBs) within RTL-designed FPGA architectures. Traditional FPGA designs face limitations in power consumption, delay, and area due to the constraints of reconfigurable circuits. The proposed architecture leverages RTL-level design capabilities to address these challenges and enables the co-design of FPGAs and ASICs. The authors evaluate the performance of 8-bit, 16-bit, and 32-bit input LBs in terms of delay, area, and synthesis feasibility. The results demonstrate that 8-bit input LBs achieve a delay of 0.68 ns with an area of 2202.48 μm<sup>2</sup>, outperforming multi-stage smaller LBs. Although 16-bit input LBs show potential for delay reduction, their synthesis demands significant time and results in a large area footprint, rendering them impractical. Synthesis of 32-bit input LBs was not feasible due to current tool limitations. These findings highlight the effectiveness of 8-bit input LBs for pattern matching tasks and emphasize the importance of application-specific optimization. The fixed routing feature of RTL-designed FPGAs facilitates the development of efficient, customizable designs tailored to specific workloads. This work contributes to the advancement of FPGA architectures, offering insights for future research on larger input LBs and their integration into high-performance applications.
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Application-Optimized FPGAs Design Using RTL-Designed FPGAs Architectures
(2025-01-01)
Sato, Tomoaki
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Murakami, Anyu
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Chivapreecha, Sorawat
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Moungnoul, Phichet
RTL-Designed Field-Programmable Gate Arrays (FPGAs) can describe FPGA functionality using Hardware Description Languages (HDLs), which means they can be easily customized to configure the FPGA. In conventional FPGAs, switches are used for routing control, making it impossible to design them using HDLs. This study leverages the customizable nature of RTL-Designed FPGAs to explore the optimal configuration of FPGAs for packet processing in computer networks. It demonstrates that a 4-input Look-Up Table (LUT) is superior to a 3-input LUT in terms of throughput and reveals that, as the number of LUT inputs increases, having 5 routing paths is more optimal than 4.
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Optimal Number of Wires for Circuits on RTLDesigned FPGAs
(2024-01-01)
Sato, Tomoaki
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Hayashihara, Yuya
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Yokota, Shione
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Chivapreecha, Sorawat
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Moungnoul, Phichet
FPGAs (Field-Programmable Gate Arrays) with reconfigurable features are used in various applications. However, circuits on FPGAs are inferior to circuits on ASICs in operating frequency, power consumption, and area. Co-design of FPGA and ASIC is one way to solve this problem. To realize this co-design, RTL-Designed FPGAs have been proposed by the authors. The features of the FPGAs are that they can be described only with HDL and that they can be realized with ordinary standard cells. Therefore, FPGAs and ASICs can be co-designed easily. Until now, the FPGAs have not been considered for optimal wiring count. In this paper, we clarify the optimum number of wires using a 4-bit adder circuit. In addition, cases in which more than that optimal number of wires is needed are discussed.
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Development of 5G Polar Experimental Kit
(2022-01-01)
Wongsa, Anusorn
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Mueadkhunthod, Krittiyaporn
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Phakphisut, Watid
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Duangthong, Chatuporn
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Puntsri, Kidsanapong
The 5G polar experimental kit is presented for learning polar codes in 5G new radio. The experimental kit is developed to demonstrate the eleven encoding processes of polar codes described in 3GPP TS 38.212 technical specification. The experimental kit provides a graphical user interface (GUI) which a user can provide any the input parameters defined in the 5G new radio. The experimental kit provides a software and a hardware for a 5G polar encoder. After the polar encoder in the software or the hardware are done, the encoding results will be displayed on the GUI along with their processes details.
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Configurable Hardware Architecture of Multidimensional Convolution Coprocessor
(2021-01-20)
Boonyuu, Geranun
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Wisayataksin, Sumek
We propose a configurable coprocessor for the convolutional neural network (CNN) that suit various models of CNN. It can operate 2D standard convolution, 2D depthwise separable convolution, 3D convolution, and a fully connected layer. The proposed processing cluster consists of 72 processing units (PUs) of half-precision floating-point to assist the main processor in embedded systems. The experimental results on Artix-7 FPGA revealed that our design has 12.16 GOPs per cluster. Moreover, this architecture was designed to be scalable for the systems with higher performance.
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IR-UWB pulse generation using FPGA scheme for through obstacle human detection
(2020-07-01)
Tantiparimongkol, Lalida
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Phasukkit, Pattarapong
This research proposes a scheme of field programmable gate array (FPGA) to generate an impulse-radio ultra-wideband (IR-UWB) pulse. The FPGA scheme consists of three parts: digital clock manager, four-delay-paths stratagem, and edge combiner. The IR-UWB radar system is designed to detect human subjects from their respiration underneath the rubble in the aftermath of an earthquake and to locate the human subjects based on range estimation. The proposed IR-UWB radar system is experimented with human subjects lying underneath layers of stacked clay bricks in supine and prone position. The results reveal that the IR-UWB radar system achieves a pulse duration of 540 ps with a bandwidth of 2.073 GHz (fractional bandwidth of 1.797). In addition, the IR-UWB technology can detect human subjects underneath the rubble from respiration and identify the location of human subjects by range estimation. The novelty of this research lies in the use of the FPGA scheme to achieve an IR-UWB pulse with a 2.073 GHz (117 MHz–2.19 GHz) bandwidth, thereby rendering the technology suitable for a wide range of applications, in addition to through-obstacle detection.
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Multiplier-less and compact FPGA implementation of Mihalas-Niebur neuron
(2019-11-01)
Kongpoon, Metha
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Leelavattananon, Kritsapon
The modified Mihalas-Niebur neuron model suitable for a compact digital implementation is presented. Based on the modified model, a multiplier-less and compact Mihalas-Niebur neuron that uses word-length optimization and bitwise shifting operators for the multiplication was designed and implemented on an FPGA. The simulation results show that the proposed neuron successfully produces all 20 prominent spiking patterns with a few FPGA resources used.
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An efficient hardware architecture of Codec2 low bit-rate speech decoder
(2019-07-01)
Wisayataksin, Sumek
Speech coding algorithms have been developed for years to digitalize human voice to a few binary bits as possible while maintaining reasonable quality. Codec2 vocoder algorithm is one of an efficient sinusoidal coding with very high compression rate down to 450 bit/s. In this paper, an efficient hardware architecture of Codec2 decoder is proposed to increase the performance of voice decoding process and reduce comprehensive tasks from a host processor. Although the sinusoidal decoding algorithm is complicated with many arithmetic operations such as the arithmetic of complex numbers, FFT, FIR filter, division, trigonometry, exponential and logarithm functions, several techniques were explored to optimize and parallelize a datapath of the proposed hardware. The implementation on Xilinx Artix-7 FPGA revealed that the proposed architecture could reduce the processing time up to 20 times, compared to the conventional Cortex-M4 CPU running with the original software.
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A programmable artificial neural network coprocessor for handwritten digit recognition
(2019-07-01)
Wisayataksin, Sumek
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Boonyuu, Geranun
This paper proposes the hardware architecture of an artificial neural network coprocessor that its structure can be programmable. The number of neurons in each layer of a feedforward network can be set by writing configuration registers. The processing unit with four MACs and the sigmoid calculation engine are connected in eight pipeline stages to enhance the processing speed. The application of handwritten digit recognition from the MNIST database was performed to verify the performance of proposed architecture. The design was developed with Verilog HDL and implemented on the Xilinx Artix-7 XC7A35T FPGA. The experimental results revealed that the speed of back-propagation learning and validation process can be up to 47 times faster than computation on ARM Cortex-A4 CPU, while the recognition rate is still the same.
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Designing of uwb pulse generation in fpga based on delay line method for human range through the wall detecting application
(2019-07-01)
Tantiparimongkol, Lalida
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Phasukkit, Pattarapong
This paper intends to present UWB generation by FPGA for further using in human detecting through the wall. In this experiment, we use method of digital circuit synthesize by Verilog coding into FPGA. Which coding method is the implementation of Delay line based theory. This experiment could produce pulse with pulse width 575ps and bandwidth of 3.83GHz. The purpose is applied for radar through the wall for human range detection application. There're experiment with human detection system which locate human movement from Doppler frequency and standard deviation. The experiment is shown at range of detection at 1m, 1.5m and 2m which the result shows output pulse from FPGA could detect human at these ranges.

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