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    Development of High Efficient LDPC Encoder for Deep Space Applications
    (2023-01-01)
    Srisupha, Thanat
    ;
    Wongsa, Anusorn
    ;
    Duangthong, Chatuporn
    ;
    Phakphisut, Watid
    In this paper, we present the design and implementation of a high efficient low-density parity-check (LDPC) encoder for deep space applications. The proposed encoder utilizes the generator matrix of CCSDS LDPC codes to simplify the encoding process and reduces the complexity of hardware implementation. The proposed encoder has two types. The first type aims to design a low-complexity architecture and flexibility. The second type presents high throughput architecture, allowing the user to choose the appropriate type according to their usage condition. The results of FPGA synthesis show that the proposed LDPC encoders achieve flexibility, low complexity, and high throughput.
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    Development of 5G LDPC Experimental Kit
    (2022-01-01)
    Srisupha, Thanat
    ;
    Mueadkhunthod, Krittiyaporn
    ;
    Phakphisut, Watid
    ;
    Khittiwitchayakul, Sirawit
    ;
    Puntsri, Kidsanapong
    In this work, we develop the 5G LDPC experimental kit to demonstrate the encoding processes of LDPC codes in 5G new radio. The experimental kit consists of a graphical user interface (GUI) and an FPGA development board. Any parameters defined in the 5G new radio can be configured and their encoding results are presented in the GUI. We also develop the 5G LDPC encoder as the software module integrated within the GUI. The user can select the software or hardware for the 5G LDPC encoder. The experimental kit is simple to use and no need any complicated setups. We believe that the experimental kit would be useful to anyone interested in the LDPC 5G NR standard.
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    Associated sectors of magnetic recording system via spatially coupled LDPC codes
    (2021-05-19)
    Khittiwitchayakul, Sirawit
    ;
    Supnithi, Pornchai
    ;
    Phakphisut, Watid
    Spatially coupled low-density parity-check (SC- LDPC) codes have emerged as promising advanced error- correcting codes (ECC) for future high-density magnetic recording (MR) systems, which require excellent error-correcting performance and acceptable practical complexity. In the traditional MR systems, the non-associated sectors are generally used, whereby two consecutive sectors are independently decoded by ECC. In this work, we propose the associated sectors of MR systems in which the information stored in the previous sectors can be requested by ECC to reinforce the decoding of the current sector. Moreover, the proposed associated sectors can mitigate the rate-loss problem of SC-LDPC codes in the MR systems. We demonstrate the bit-error-rates (BERs) of SC-LDPC codes in the bit-patterned media magnetic recording (BPMR) systems with non-associated sectors and associated sectors. The simulation results show that the associated sectors help achieve significant performance gains compared to the non-associated sectors.
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    Read Voltage Optimization in MLC NAND Flash Memory via the Density Evolution
    (2019-04-01)
    Duangthong, Chatuporn
    ;
    Phakphisut, Watid
    ;
    Supnithi, Pornchai
    The multi-level-cell (MLC) NAND flash memory can typically use multiple reads for obtaining soft information for the LDPC decoder. The multiple reads give the soft information which is quantized to a certain level. The major challenge is that the read voltages must be precisely selected to provide better soft information. In the previous work, the read voltages are selected so that the soft information has the maximum mutual information (MMI). However, the error-correction capability of LDPC decoder is not considered. Therefore, in this work, we analyze the performance of LDPC decoder by density evolution whereby the soft information is quantized. Then the optimal read voltages for given LDPC codes are obtained. As a result, for a regular LDPC code with the read voltages optimized by density evolution can provide the lower BER performance compared with the MMI technique.
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    A simple algorithm for a high code rate LDPC parity matrix design
    (2011-12-26)
    Timakul, Sekson
    ;
    Choomchuay, Somsak
    This paper presents a simple method in designing a parity matrix of low density parity check codes. According to its use the use of arithmetic sequence is ideal for high rate code with no existing of cycle 4. The design is applicable to array code, modified array code, and quasi cyclic code. Upon the investigation, the designed code has delivered a similar BER-SNR performance when compared with that of more complicate designed matrices. © 2011 IEEE.
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    Structured LDPC codes to reduce pseudo cycles for turbo equalization in perpendicular magnetic recording
    (2011-01-01)
    Supnithi, Pornchai
    ;
    Phakphisut, Watid
    ;
    Singhaudom, Wicharn
    Low-density parity-check (LDPC) codes are typically designed to avoid the length-4 cycles to ensure acceptable levels of performance. However, the turbo equalization, which relies on an interaction between an inner code such as an LDPC code and a soft-output Viterbi algorithm (SOVA) detector, exhibits a performance degradation due to the pseudo cycles. In this paper, we propose an interleaved modified array code (IMAC) that can reduce the number of pseudo cycles, hence, improving the gains from the iterative processing technique. The modification is made on the existing array-based LDPC codes named modified array codes (MAC) by introducing an additional interleaving matrix to the parity-check matrix. Simulation results on the perpendicular magnetic recording channels (PMRC) demonstrate that the IMAC outperforms both the MAC and the previously proposed random interleave array (RIA) codes for the partialresponse targets under consideration. In addition, a subblock-based encoder design is proposed to reduce the encoding complexity of the IMAC and when compared with the RIA code, the IMAC exhibits a lower encoding complexity, and still maintains a comparable level of the decoding complexity. Copyright © 2011 The Institute of Electronics, Information and Communication Engineers.
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    Low-complexity turbo equalization using E-BAD detector combine with LDPC codes for high-density magnetic recording
    (2008-10-06)
    Moodleah, S.
    ;
    Benjangkaprasert, C.
    ;
    Sangaroon, O.
    ;
    Udomsripaiboon, T.
    ;
    Sa-Ad, S.
    An extend bi-directional arbitrated decision feedback equalizer (E-BAD) was developed from BAD which shown that performance is improved at low error rate. BAD detector can be replaced for the high-complexity detector in turbo equalization for a coded magnetic recording channel which the performance is closed. This paper considers a performance evaluation of E-BAD detector in turbo equalization with selected LDPC code which the performance is improved while keep low-complexity structure. ©2008 IEEE.