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Efficient Design of Read Voltages and LDPC Codes in NAND Flash Memory Using Density Evolution
(2023-01-01)
Duangthong, Chatuporn
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Phakphisut, Watid
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Wardkein, Paramote
Low-density parity-check (LDPC) codes play an important role in the reliability enhancement of commercial NAND flash memory. Unfortunately, due to the requirement of the reading speed of NAND flash memory, the LDPC decoder will not obtain precise soft information to achieve high error-correcting capability. In this work, we use a density evolution (DE) algorithm to reveal the decoding threshold of the LDPC decoder affected by the read voltages. We propose the efficient design of read voltages so that the LDPC decoder has the lowest decoding threshold. Therefore, this method can guarantee that the designed read voltages are suitable for a given LDPC code. Moreover, since we found that the designed read voltages are related to the structure of the LDPC code, the joint design of the read voltages and LDPC code is then proposed to achieve the capacity of NAND flash memory. The simulation results demonstrate that our proposed design significantly improves the frame error rate (FER) performance of NAND flash memory.
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Joint design of channel output quantizer and LUT-Based LDPC decoder
(2021-05-19)
Duangthong, Chatuporn
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Supnithi, Pornchai
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Phakphisut, Watid
Recently, the LUT-based LDPC decoder has been designed by maximizing mutual information, where the performances of channel output quantizer and LUT-based decoder are considered separately. In this work, we propose the joint design of the channel output quantizer and LUT-based decoder. Our joint design aims to minimize the error probability of LDPC decoding through the density evolution algorithm. We found that the joint design outperforms the previous work at the waterfall region.
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EXIT Chart Analysis of Protograph-based LDPC Codes for Unequal Power Two-User Gaussian Multiple Access Channel
(2020-07-01)
Khittiwitchayakul, Sirawit
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Phakphisut, Watid
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Supnithi, Pornchai
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Min Myint, Lin Min
In this work, we analyze the theoretical performances of protograph-based LDPC codes for unequal power two-user Gaussian multiple access channel (GMAC) by using Extrinsic information transfer (EXIT) chart. We show that the decoding performances of LDPC codes for two-users are improved significantly when the transmitted power of user increases. Moreover, we present the design of protograph structures of the LDPC codes for unequal power two-user GMAC by using the differential evolution (DE). The results show that the designed LDPC codes outperform the traditional LDPC codes.
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Sliding-window processing of turbo equalization for partial response channels
(2019-04-01)
Khittiwitchayakul, Sirawit
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Phakphisut, Watid
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Supnithi, Pornchai
Spatially coupled low-density parity-check (SC-LDPC) codes are the attractive candidates for the application requiring a practical constraint on the latency and complexity. In previous works, the turbo equalization consisting the SC-LDPC window decoder and Bahl-Cocke-Jelinek-Raviv (BCJR) detector is used to tackle the inter-symbol interferences (ISIs) in the magnetic recording systems. However, the prior works consider only the SC-LDPC codes which replace the conventional LDPC block codes. In this work, we propose the modification of turbo equalization processing whereby both the SC-LDPC decoder and BCJR detector operate using the sliding window. The results show that the proposed turbo equalization schemes used in the partial response (PR) channel can provide better bit error rate (BER) performances than the conventional turbo equalization.
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A simple design for large girth LDPC matrix
(2017-07-01)
Choomchuay, Somsak
This paper describes an alternative method for designing regular quasi-cyclic LDPC codes with large girths. The permutation matrix was designed based on the geometric sequence and prime number field. The design starts with a portion of the full-range matrix with column weight of 3. With a decided code rate, elements in the rows are extended by adding a certain column of the same full-range matrix into the designing matrix. Resulted codes can offer relatively good performance compared to the published literatures.
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An implementation of low-density MDS array codes for data protection in distributed network data storage system
(2016-09-07)
Puttarak, Nattakan
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Kaewprapha, Phisan
We present an implementation of disk arrays(RAIDs) in distributed networked data storage environment by applying an error-correcting to accommodate fault tolerance feature. Any of the current state-of-the-art distributed file systems, such as MooseFS [1], can be used as an underlying data space where low density-MDS (Maximum distance separable-Low density parity check) array codes [3] is used as a logical protection layer implemented through FUSE interface (File System In User Space). The redundancy/parity scheme is based on graph structures leading to an MDS code, then can be simply implemented in a parity matrix (H matrix) of an LDPC code. The ability of error correction and data recovery is shown as the bit-error rate (BER) has been investigated. It achieves the same trend compared to the simulation results in [3]. The low-density MDS array code can mitigate hardware failure at higher disk space efficiency comparing to the repetition code.
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A simple parity check matrix LDPC code for perpendicular magnetic recording channels
(2013-09-02)
Timakul, Sekson
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Choochuay, Somsak
In LDPC code design, the structure of code's parity check matrix can be very crucial to code performance. In this paper, we have investigated a simple designed parity check matrix when the code is applied to a PMR channel of a storage system. Belief propagation algorithm and min-sum algorithm are two major decoding algorithms used to benchmarked the code's merits. Additive white Gaussian noise channel (AWGN) and perpendicular magnetic recording (PMR) channel with SISO equalizer in PR2 target are the conditions of our investigation. The LDPC code itself is a modified array type. Its construction fairly simple compared to normal array and quasi-cyclic code. We used two decision variables to define the permutation matrix. A method proposed by Tanner's et.al had been adapted to the modified array code. The decoders have been tested for 5 and 20. iterations. SNR versus BER and BLER were measured. © 2013 IEEE.
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Construction of quasi-cyclic LDPC codes form SFT structure and cyclic shift
(2011-12-01)
Timakul, Sekson
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Choomchuay, Somsak
This paper presents an alternative a method for designing a parity matrix of low density parity check codes. The proposed method can be viewed as a generalized version of Sridara-Fuja-Tanner (SFT) technique which is ideal for regular quasi cyclic code design. Upon the current investigation, the designed code has delivered a comparable BER-SNR performance when compared with that of more complicate designed matrix. The designed code offers similar performance when compared with Sridara-Fuja-Tanner code and Quadratic Congruences structure. In additions, the resulted matrix also has a desirable structure that it suits well the hardware implementation. © 2011 IEEE.
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Quasi Cyclic-LDPC codes based on PEG algorithm with maximized girth property
(2011-12-01)
Prompakdee, Patanasak
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Phakphisut, Watid
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Supnithi, Pornchai
In this paper, we propose a method to construct parity-check matrices of Quasi Cyclic (QC) LDPC codes based on the progressive edge-growth (PEG) algorithm with maximized girth property. The proposed algorithm can eliminate short cycles and improve the decoding performance. Simulation results illustrate that the codes constructed with the proposed algorithm have superior performance to the previous PEG-QC codes over the additive white Gaussian noise (AWGN) channel. At the BER of 10 <sup>7</sup>, the coding gain of 0.005 dB. © 2011 IEEE.
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A design of nonprime block irregular LDPC codes via CRT
(2010-12-01)
Chusin, Chalit
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Prasartkaew, Chutima
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Timakul, Sekson
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Choomchuay, Somsak
This paper presents a new design of irregular LDPC codes that supports arbitrary block length. We propose the efficient construction method when nonprime size sub-matrices are used. The problem where GCD(L<inf>1</inf>,L <inf>2</inf>) that left unsolved has been tackled. We also consider the case GCD(L<inf>1</inf>,L<inf>2</inf>)=1 but L<inf>1</inf> or L<inf>2</inf> is a nonprime number. The results show that our designed codes have superior performance compared to MAC. The resulted codes still hold the attractive properties of LDPC codes. The performances of interleaved codes are higher than noninterleaved codes and it goes higher as SNR is increased. ©2010 IEEE.

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