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    Pixel-based foreground detection in repetitive time-series region
    (2019-01-01)
    Rattanapitak, Wirat
    ;
    Wangsiripitak, Somkiat
    Currently, many state-of-the-art background subtraction techniques cannot deal properly with the area of periodic changing background, while some continue classifying them as foreground at intervals, others simply mask that area as a non-region of interest. To cope with this issue, a novel method of detecting repetitive temporal patterns based on the image sequences was proposed in this paper. The main emphasis of the proposed approach is on classifying those pixels as a background and identifying foreground objects in their relevant areas. As for the foreground detection, a model of time series pattern found in each pixel is individually built first; and then, any changes beyond the allowance of model periodicity are then determined as foreground objects. The proposed method could be used and run in parallel with any state-of-the-art background subtraction technique, allowing more accurate foreground-background segmentation. Experimental results showed that using Y channel, the proposed method of detecting time-series background area could achieve 92.9% of recall rate with less than 1% false positives. The recall of foreground detection in an area of repetitive time-series pattern was about 87%; while F-measure was about 0.73 on average. The false positives of foreground detection were also less than 1%. Accordingly, the proposed time-delay detection technique could significantly help to suppress the foreground error on time series background area, especially during the change from one sub-pattern to another which causes a camera sensor to capture both sub-pattern values in one frame. Performance comparison with state-of-the-art methods showed that our proposed method was able to reduce 80% of the average false alarm and improve F-measure to 28% while the computational efficiency was reduced by only 1%.
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    Character-based indexing using inverted lists
    (2009-12-01)
    Knancome, Chouvalit
    ;
    Boonjing, Veera
    This research article presents a new character-based indexing algorithm which generates all locations of target text to the inverted list in existed bit form. This algorithm is efficiently to search in the case of streaming character input that needs to immediately response. © 2009 IEEE.
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    PAMELA: Pattern matching engine with Limited-time updAte for NIDS/NIPS
    (2009-01-01)
    Thinh, Tran Ngoc
    ;
    Kittitornkun, Surin
    ;
    Tomiyama, Shigenori
    Several hardware-based pattern matching engines for network intrusion/prevention detection systems (NIDS/NIPSs) can achieve high throughput with less hardware resources. However, their flexibility to update new patterns is limited and still challenging. This paper describes a PAttern Matching Engine with Limited-time updAte (PAMELA) engine using a recently proposed hashing algorithm called Cuckoo Hashing. PAMELA features on-the-fly pattern updates without reconfiguration, more efficient hardware utilization, and higher performance compared with other works. First, we implement the improved parallel exact pattern matching with arbitrary length based on Cuckoo Hashing and linkedlist technique. Second, while PAMELA is being updated with new attack patterns, both stack and FIFO are utilized to bound insertion time due to the drawback of Cuckoo Hashing and to avoid interruption of input data stream. Third, we extend the system for multi-character processing to achieve higher throughput. Our engine can accommodate the latest Snort rule-set, an open source NIDS/NIPS, and achieve the throughput up to 8.8 Gigabit per second while consuming the lowest amount of hardware. Compared to other approaches, ours is far more efficient than any other implemented on Xilinx FPGA architectures. Copyright © 2009 The Institute of Electronics, Information and Communication Engineers.
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    FPGA-based cuckoo hashing for pattern matching in NIDS/NIPS
    (2007-01-01)
    Tran, Thinh Ngoc
    ;
    Kittitornkun, Surin
    Pattern matching for network intrusion/prevention detection demands exceptionally high throughput with recent updates to support new attack patterns. This paper describes a novel FPGA-based pattern matching architecture using a recent hashing algorithm called Cuckoo Hashing. The proposed architecture features on-the-fly pattern updates without reconfiguration, more efficient hardware utilization, and higher throughput. Through various algorithmic changes of Cuckoo Hashing, we can implement parallel pattern matching on SRAM-based FPGA. Our system can accommodate the newest Snort rule-set, an open source Network Intrusion Detection/Prevention System, and achieve the highest utilization in terms of SRAM per character and Logic Cells per character at 15.63 bits/character and 0.033 Logic Cells/character, respectively on major Xilinx Virtex FPGA architectures. Compared to others, ours is more efficient than any other Xilinx FPGA architectures. © Springer-Verlag Berlin Heidelberg 2007.