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Two CMOS Wilkinson Power Dividers Using High Slow-Wave and Low-Loss Transmission Lines
(2024-08-01)
Pakasiri, Chatrpol
;
Teng, Wei Sen
;
Wang, Sen
This work presents two Wilkinson power dividers (WPDs) using multi-layer pseudo coplanar waveguide (PCPW) structures. The PCPW-based WPDs were designed, implemented, and verified in a standard 180 nm CMOS process. The proposed PCPW features high slow-wave and low-loss performances compared to other common transmission lines. The two WPDs are based on the same PCPW structure parameters in terms of line width, spacing, and used metal layers. One WPD was realized in a straight PCPW-based layout, and the other WPD was realized in a meandered PCPW-based layout. Both the two WPDs worked up to V-band frequencies, as expected, which also demonstrates that the PCPW guiding structure is less susceptible to the effects of meanderings on the propagation constant and characteristic impedance. The meandered design shows that the measured insertion losses were about 5.1 dB, and its return losses were better than 17.5 dB at 60 GHz. In addition, its isolation, amplitude imbalance, and phase imbalance were 18.5 dB, 0.03 dB, and 0.4°, respectively. The core area was merely 0.2 mm × 0.23 mm, or 1.8 × 10−3λ<inf>o</inf>2.
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Compact Wilkinson Power Divider with Common Inductor on the IPD Process
(2021-01-01)
Pakasiri, Chatrpol
;
Wang, Sen
This paper presents a Wilkinson power divider using a common inductor. The lumped topology uses the inherently inductive loss of the inductor as a part of the design, so the conventional resistor for high isolation can be omitted. Therefore, low-loss and high-isolation performances of the compact circuit were achieved. The proposed 2.5-GHz divider was implemented on a silicon-based integrated passive device process. Measurement of the prototype chip had a reflection coefficient below 18 dB at all ports, an insertion loss of 0.5 dB and isolation above 28 dB. The chip size is merely 0.011λ o× 0.019λ o.
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Compact Wilkinson Power Divider Using Composite Right/Left-Handed Transmission Line on CMOS Process
(2020-03-01)
Nithiporndecha, Kittipong
;
Wang, Sen
;
Pakasiri, Chatrpol
This paper shows the design and analysis of CMOS Wilkinson power divider using composite right/left-handed transmission lines. The effects of lossy components in the circuit are also analyzed. The circuit is then implemented on a 0.18-μm CMOS process. The return losses are less than -16 dB, the isolation is better than -26 dB, and the insertion losses are better than -5.15 dB at the frequencies of interest. Its chip size is 0.5 mm2 (9.9e-5λ<inf>o</inf>2) including testing pads.
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Dual-band compact wilkinson power divider using common inductor and complex load
(2020-01-01)
Pakasiri, Chatrpol
;
Wang, Sen
A 1.8/2.4-GHz dual-band compact Wilkinson power divider was designed and implemented using an integrated passive device process. The design used a common inductor to match impedance in the even mode. The common inductor replaced two shunt inductors in the circuit so the circuit size was reduced. An additional complex load was then used for matching impedance in the odd mode. The circuit measurements showed reflection at all ports better than -11.9 dB, isolation at the output ports better than -14 dB and transmission coefficient better than -4.3 dB, at both operating frequencies. The circuit occupied only only 0.036λο λ0.018λο at the higher operating frequency at the higher operating frequency.

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