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An Interconnect Topology Optimization by Tree Transformation
Author(s)
Arungsrisangchai, Itthichai
Tsukiyama, Shuji
Shirakawa, Isao
Date Issued
January 1, 2002
Type
Article
Abstract
Since the interconnect delay has become the dominating factor in circuit performance, and the demands for a better delay-minimization router are very high. In this paper, we propose an algorithm for finding an interconnect tree of a net that minimizes a weighted sum τ of delays to all sinks, where the weight assigned to a sink represents a criticality of the delay to the sink. The algorithm starts from a Steiner tree and repeats a tree transformation while the change of τ is monitored. Experimental results are also shown, which demonstrates the effectiveness of the algorithm, especially for MCM and PCB routing. © 2002, The Japan Institute of Electronics Packaging. All rights reserved.
Citation
Journal of the Japan Institute of Electronics Packaging, 5(4), 342-348, 2002