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A hardware design of MS/MMS-based LDPC decoder
Author(s)
Tanyanon, Itsara
Choomchuay, Somsak
Date Issued
December 1, 2012
Type
Conference Paper
Abstract
This paper presents a hardware design of a LDPC decoder where Min-Sum (MS) and Modified Min-Sum (MMS) algorithm has been investigated. The parity check matrix is complied with IEEE 802.11n recommendation (code rate of 0.5, 648 bits block length). Verilog description language is employed for Xilinx XC2VP30-7 FPGA. With the matrix reordering technique, the final design shows that the data rate of 127 Mbps could be achieved when the pipeline stages are used. © 2012 IEEE.
Citation
2012 IEEE International Conference on Electron Devices and Solid State Circuit Edssc 2012, 2012