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Defect distribution and yield analysis technique on silicon wafer
Author(s)
Date Issued
January 1, 2014
Type
Conference Paper
Abstract
This paper presents the defect distribution and yield analysis on silicon wafer. The generation and recombination lifetime were the key parameters and obtained from the current- voltage and the capacitance-voltage of diode characteristics for forward bias. Then 3D contour maps were plotted as defect distribution and can be analyzed for the whole wafer which is useful for the yield analysis of the defects that were caused from fabrication process. © (2014) Trans Tech Publications, Switzerland.
Citation
Advanced Materials Research, 911, 271-275, 2014