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A FPGA design of AES core architecture for portable hard disk
Author(s)
Thongkhome, Khanob
Thanavijitpun, Chalermwat
Choomchuay, Somsak
Date Issued
July 21, 2011
Type
Conference Paper
Abstract
This paper describes a high effective AES core hardware architecture for implementing it to encrypt/decrypt the data in portable hard disk drive system that apply to effectively in the terms of speed, scale size and power consumption to comply with minimum speed of 5 Gbps (USB3.0). We proposed the 128 bits data path of two different AES architectures design, Basic Iterative AES, which reuses the same hardware for all the ten iterations and, One Stage Sub Pipelined AES, with one stage of outer pipelining in the data blocks that both of them are purely 128 bits data path architecture that different from the previous public paper. The implementation result on the targeted FPGA, the basic iterative AES encryption can offer the throughput of 3.85 Gbps at 300 MHz and one stage sub pipelined AES can offer the throughput to increase the efficiency of 6.2 Gbps at 481 MHz clock speed. © 2011 IEEE.
Citation
Proceedings of the 2011 8th International Joint Conference on Computer Science and Software Engineering Jcsse 2011, 223-228, 2011