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A current-mode CMOS sample-and-hold circuit for ADC
Author(s)
Mahatthumthanant, Phinet
Kamsri, Thawatchai
Sungkabunchoo, Tiparat
Date Issued
December 1, 2006
Type
Conference Paper
Abstract
This paper presents a current-mode sample-and-hold circuit using 0.5μm CMOS technology. The input signal is sampled using a current subtracter and a half wave rectifier instead of a sampling switch used in the conventional sample-and-hold circuit. As a result, the switch feedthrough error is eliminated. The proposed circuit achieves high sampling frequency up to 100MHz and high accuracy. The performances of the proposed circuit are demonstrated by PSPICE simulation results. © 2006 ICASE.
Citation
2006 SICE Icase International Joint Conference, 5758-5761, 2006