Efficient scheduling for design exploration with imprecise latency and register constraints

Chantrapornchai, Chantana; Surakumpolthorn, Wanlop; Sha, Edwin

doi:10.1007/978-3-540-30121-9_25

Efficient scheduling for design exploration with imprecise latency and register constraints

Author(s)

Chantrapornchai, Chantana

Surakumpolthorn, Wanlop

Sha, Edwin

Date Issued

January 1, 2004

Type

Article

DOI

10.1007/978-3-540-30121-9_25

Abstract

In archiectural synthesis, scheduling and resource allocation are important steps. During the early stage of the design, imprecise information is unavoidable. Under the imprecise system characteristics and constraints, this paper proposes a polynomial-time scheduling algorithm which minimizes both functional units and registers while scheduling. The algorithm can be used in design exploration for exploring the trade-off between latency and register counts and selecting a solution with satisfactory performance and cost. The experiments show that we can achieve a schedule with the same acceptable degree while saving register upto 37% compared to the traditional algorithm. © Springer-Verlag Berlin Heidelberg 2004.

Citation

Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, 3207, 259-270, 2004