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A 1.3-V, 9.1μW wide-dynamic range logarithmic amplifier for cochlear implant system
Author(s)
Sundarasaradula, Yuwadee
Thanachayanont, Apinunt
Date Issued
January 1, 2014
Type
Conference Paper
Abstract
This paper presents the design and realization of a low-noise, low-power, wide-dynamic-range CMOS logarithmic amplifier for cochlear implant system in a standard 0.18μm CMOS technology. The proposed logarithmic amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. The overall circuit consumes only 9.1 μW from a 1.3 V single power supply voltage. The simulated input dynamic range is 80 dB, which covers the input amplitudes ranging from 10 μV to 100 mV. The simulated bandwidth of the amplifier is from 50 Hz to 24 kHz. The simulated total input-referred noise is 4.81 μV, integrated from 100 Hz to 10 kHz. © 2014 IEEE.
Citation
2014 11th International Conference on Electrical Engineering Electronics Computer Telecommunications and Information Technology Ecti Con 2014, 2014