Substrate bias effects on Drain Induced Barrier Lowering (DIBL) in short channel NMOS FETs

Abstract

The substrate biasing characteristics of the Drain-Induced Barrier Lowering (DIBL) effects in short-channel NMOS devices with n+ polysilicon gate that fabricated at TMEC by 0.8 CMOS technology were presented. It was found that by increasing the substrate bias form -1 to -5V, DIBL in NMOS devices with mask channel length (L) from 0.6 to 3.0 micron shows the interesting feature. As the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias and then decreased as the channel length decreased further for the range of L# 0.6 micron. But the DIBL increased with increasing substrate bias for the length of L between 0.8 and 1.2 micron. And almost neglected the substrate bias effect for the range of L > 1.2 micron. The substrate bias effect on subthreshold DIBL coefficient (ETAb) is approximately 3.5, 7.0, 8.0 and 0.7 mV/V for L of 0.8, 1.0, 1.2 and 3.0 micron respectively. Whereas the subthreshold DIBL coefficient (ETA0)is around 44, 10, 5 and 1.25 mV/V respectively. This change in DIBL with substrate bias for a short channel device can be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Design considerations of the channel doping profile in short channel NMOS device for substrate bias based on improving the punchthrough and DIBL are also briefly discussed. © 2009, INSInet Publication.