Analog operation in CMOS latch circuit for reducing dynamic power dissipation

Dejhan, K.; Cheevasuvit, F.; Tipsuwanporn, V.; Trisuwannawat, T.; Prommas, E.

doi:10.1109/MWSCAS.1992.271266

Analog operation in CMOS latch circuit for reducing dynamic power dissipation

Author(s)

Dejhan, K.

Cheevasuvit, F.

Tipsuwanporn, V.

Trisuwannawat, T.

Prommas, E.

Date Issued

January 1, 1992

Type

Conference Paper

DOI

10.1109/MWSCAS.1992.271266

Abstract

Many approaches to study of analog operation in CMOS VLSI. This paper is focused on finding an analog operation using pMOS transistor which is used to control the variation of dynamic power dissipation of the CMOS static latch circuit. The results have been simulated using SPICE under 1.2μm HCMOS3 technology.

Citation

Midwest Symposium on Circuits and Systems, 1992-August, 544-547, 1992