Efficient pass-pipelined VLSI architecture for context modeling of JPEG2000

Mathiang, Khomkris; Chitsobhuk, Orachat

doi:10.1109/APCC.2007.4433501

Efficient pass-pipelined VLSI architecture for context modeling of JPEG2000

Author(s)

Mathiang, Khomkris

Chitsobhuk, Orachat

Date Issued

December 1, 2007

Type

Conference Paper

DOI

10.1109/APCC.2007.4433501

Abstract

In this paper, a design of pass-pipelined architecture for context modeling implemented on FPGA is proposed. The architecture is separated into 4 pipelined stages. As a result, the processing time and the critical path delay can be reduced while the multiple symbol context pairs are allowed to be generated simultaneously. Moreover, dual memories and data multiplexer are employed in order to accelerate the memory access. The proposed pass-pipelined architecture can process with the speed greater than 100 MHz and can generate up to 22 context-data pairs in one clock cycle. ©2007 IEEE.

Citation

2007 Asia Pacific Conference on Communications Apcc, 63-66, 2007