An overlapping Min-Sum LDPC decoder for IEEE 802.11n

Timakul, Sekson; Tanyanon, Itsara; Choomchuay, Somsak

doi:10.1109/ISPACS.2010.5704671

An overlapping Min-Sum LDPC decoder for IEEE 802.11n

Author(s)

Timakul, Sekson

Tanyanon, Itsara

Choomchuay, Somsak

Date Issued

December 1, 2010

Type

Conference Paper

DOI

10.1109/ISPACS.2010.5704671

Abstract

This paper presents overlapping techniques designed for a compact hardware LDPC decoder with MS algorithm. The design is applicable to IEEE 802.11n standard. We elaborate how to reduce hardware and cycle time between row and column operation. The hardware utilization can be better enhanced and 16-40% cycle time reduction compared to a non-overlapping decoder can be achieved. © 2010 IEEE.

Citation

Ispacs 2010 2010 International Symposium on Intelligent Signal Processing and Communication Systems Proceedings, 2010