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Two-Dimensional Error Correction Code for Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) Caches
Author(s)
Date Issued
September 1, 2022
Type
Article
Abstract
Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) is an emerging nonvolatile memory (NVM) technology that can replace conventional cache memory in computer systems. STT-RAM has many desirable properties such as high writing and reading speed, non-volatility, and low power consumption. Since the cache requires a high speed of writing and reading speed, a single-error correction and double error detection (SEC-DED) are applicable to improve the reliability of the cache. However, the process variation and thermal fluctuation of STT-MRAM cause errors. For example, writing ‘1’ bits has more errors than writing ‘0’ bits. We then design the weight reduction code to reduce the error caused by writing ‘1’ bits. Moreover, the performance of an SEC-DED code is improved by constructing an SED-DED code as the product code. The simulation results demonstrate that the two-dimensional error correction code consisting of product code and weight reduction code is roughly 5:67×10-4 lower than the SEC-DED code when the error rate of writing ‘1’ bits is equal to 6 ×10-3.
Citation
Ecti Transactions on Computer and Information Technology, 16(3), 237-246, 2022