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CMOS class-AB voltage-mode multiplier
Author(s)
Boonchu, Boonchai
Surakampontorn, Wanlop
Date Issued
December 1, 2005
Type
Conference Paper
Abstract
A novel circuit configuration for a CMOS voltage-mode four-quadrant analog multiplier is described. It is based on square law characteristic of MOS transistor and class-AB amplifier. The multiplier achieves a linearity of 1.1%, -3dB bandwidth of 35MHz, and a total harmonic distortion of 0.76%. The power consumption is 1.5mW. © 2005 IEEE.
Citation
Iscit 2005 International Symposium on Communications and Information Technologies 2005 Proceedings, I, 1489-1492, 2005
Subjects