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A low voltage tristate buffer with complementary BiCMOS charge pump
Author(s)
Suriyaammaranon, Chatpong
Dejhan, Kobchai
Date Issued
January 1, 2004
Type
Article
Abstract
A novel high speed, low voltage BiCMOS instate buffer is presented and its performance characteristics are investigated by using PSPICE simulation. The results obtained are compared with a general CMOS and a couple of previous BiCMOS instate buffer circuits which are conventional BiCMOS and complementary BiCMOS trislate buffer circuits. It is shown that the proposed BiCMOS instate buffer circuit outperforms other previous instate buffer circuits. At lower supply voltage, the proposed circuit has been shown more advantageous speed over previous circuits and it guarantees speed advantage over previous circuits even supply voltage application is at 1.5 volt. The pass transistor technique with a single MOS transistor driving is used to improve the driving capability. Furthermore, a complementary BiCMOS charge pump technique is used to eliminate the voltage loss due to base-emitter turn on voltage and to enhance the driving capability. With the positive and negative charge pump, it can be realized a high speed at low voltage with full swing operation without performance degradation due to shunt CMOS circuit as same as previous complementary BiCMOS instate buffer circuit.
Citation
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, E87-A(7), 1781-1787, 2004