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100-MHz CMOS direct digital synthesizer with 10-bit DAC
Author(s)
Meenakarn, C.
Thanachayanont, A.
Date Issued
January 1, 2002
Type
Conference Paper
Abstract
This paper describes the design and implementation of an integrated direct digital synthesizer with a 10-bit on-chip digital-to-analog converter using a 0.5-μm CMOS technology. The DDS chip operates at 100-MHz maximum clock frequency under 3.3-V supply voltage, with 32-bit frequency, 12-bit phase and 10-bit amplitude resolution. The chip provides sinusoidal, sawtooth, ramp, square and random waveforms with phase and frequency modulation, and power-down function, occupies 12-mm2 die area, and dissipates 0.4 W at 100-MHz clock rate. At 25-MHz sinusoidal output, the measured worst-case spurious noise is -65 dBc and the phase noise is -119 dBc/Hz at 100-kHz frequency offset.
Citation
IEEE Asia Pacific Conference on Circuits and Systems Proceedings Apccas, 2, 385-388, 2002