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An efficient hardware architecture of Codec2 low bit-rate speech decoder
Author(s)
Date Issued
July 1, 2019
Type
Conference Paper
Abstract
Speech coding algorithms have been developed for years to digitalize human voice to a few binary bits as possible while maintaining reasonable quality. Codec2 vocoder algorithm is one of an efficient sinusoidal coding with very high compression rate down to 450 bit/s. In this paper, an efficient hardware architecture of Codec2 decoder is proposed to increase the performance of voice decoding process and reduce comprehensive tasks from a host processor. Although the sinusoidal decoding algorithm is complicated with many arithmetic operations such as the arithmetic of complex numbers, FFT, FIR filter, division, trigonometry, exponential and logarithm functions, several techniques were explored to optimize and parallelize a datapath of the proposed hardware. The implementation on Xilinx Artix-7 FPGA revealed that the proposed architecture could reduce the processing time up to 20 times, compared to the conventional Cortex-M4 CPU running with the original software.
Citation
Proceeding 5th International Conference on Engineering Applied Sciences and Technology Iceast 2019, 2019