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A 32 bits architecture for an AES system
Author(s)
Pongyupinpanich, S.
Phathumvanh, S.
Choomchuay, S.
Date Issued
December 1, 2004
Type
Conference Paper
Abstract
This paper describes a compact 32 bits architecture developed for the Rijndael ciphering/decyphering system. The implementation is complied with NIST Advanced Encryption standard. The design processes 128-bit block data with 128-bit key. For the area-saving implementation, the field inversion block and the key scheduling circuits are shared by both the encryption and decryption process.
Citation
IEEE International Symposium on Communications and Information Technologies Iscit 2004, 1, 70-73, 2004