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FPGA based-IC design for 3-phase PWM inverter with optimized space vector modulation schemes
Author(s)
Date Issued
October 31, 2000
Type
Conference Paper
Abstract
This paper presents a novel idea to integrate three of the space vector modulation (SVM) schemes, including the alternating zero sequence, the symmetric sequence and the bus clamped scheme, in a single FPGA chip which provides many advantages. Flexibility, reliability and a very compact system are obviously obtained from this designed chip. Moreover, faster design and verification time, and design change without penalty are also benefits resulting from FPGA-based IC design. The optimized SVM schemes, frequencies and programmable deadtime that is used to adjust output signals are obtained through either 4x4 keypad or microprocessor port.
Citation
Proceedings of the International Conference on Microelectronics Icm, 2000-October, 285-288, 2000